FPGA/corundum
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393 Commits 1 Branch 0 Tags
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6 Commits

Author SHA1 Message Date
Alex Forencich
90959b8795 Add default_nettype none and resetall directives 2021-10-20 17:49:30 -07:00
Alex Forencich
e4508b242f Update example designs 2021-08-02 18:36:25 -07:00
Alex Forencich
ccc44d7dbb Use 64 bit BARs in example designs 2021-06-16 23:23:53 -07:00
Alex Forencich
062495b780 Remove redundant parameter PCIE_EXT_TAG_ENABLE 2021-02-25 18:20:08 -08:00
Alex Forencich
8294eecd65 Remove redundant parameter PCIE_TAG_WIDTH 2021-02-25 18:10:59 -08:00
Alex Forencich
5dbb771958 Add AU280 AXI example design 2020-07-12 11:42:48 -07:00