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21 Commits

Author SHA1 Message Date
Alex Forencich
2ce89aec09 Use generate blocks for Ethernet FCS computation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 19:52:55 -07:00
Alex Forencich
5f39d6ece6 Improve internal encoding to simplify logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 17:32:43 -07:00
Alex Forencich
2601127679 Remove unnecessary zeroing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 14:09:09 -07:00
Alex Forencich
ebd5f04e2d Remove unnecessary resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 10:14:54 -07:00
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
5494f3b678 Rewrite resets 2021-10-15 23:33:35 -07:00
Alex Forencich
3684ccafb2 Make use of blocking statements consistent 2019-06-15 16:56:45 -07:00
Alex Forencich
296744b37e Make use of blocking statements consistent 2019-06-12 23:31:03 -07:00
Alex Forencich
6eff2f0030 Decouple transmit PTP tag enable and transmit PTP timestamp enable 2019-06-09 22:03:24 -07:00
Alex Forencich
2794c315e8 Fix synthesizer complaints 2019-06-08 17:36:09 -07:00
Alex Forencich
82fe5a6bdd Add PTP timestamp capture logic to MACs 2019-06-07 16:38:36 -07:00
Alex Forencich
659aa67481 Pack start packet strobes into the same signal 2019-06-06 17:13:14 -07:00
Alex Forencich
585ccefa15 Add TX underflow error signal 2019-03-26 12:42:08 -07:00
Alex Forencich
0efb135b7a Fix STATE_WAIT_END 2019-03-25 15:06:45 -07:00
Alex Forencich
e644ce3895 Add start packet strobe timing outputs to MAC modules 2019-01-31 17:00:23 -08:00
Alex Forencich
9ae60dcd9a Simplify lane swapping code 2019-01-22 14:22:01 -08:00
Alex Forencich
6238ed5755 Report error for invalid encoding 2019-01-22 14:19:43 -08:00
Alex Forencich
e784900050 Remove unused code 2019-01-22 14:18:27 -08:00
Alex Forencich
ebe31e811c Use parameters for control characters 2018-11-08 13:15:47 -08:00
Alex Forencich
d2fedc4134 Rename ports 2018-11-07 22:35:06 -08:00
Alex Forencich
de69975872 Add AXI stream XGMII RX and TX modules and testbenches 2018-10-23 23:34:43 -07:00