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26 Commits

Author SHA1 Message Date
Alex Forencich
2d5e82f42a apps: Fix application module symbol search path to include core mqnic module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-25 00:48:56 -07:00
Alex Forencich
2bd8350276 Add RX queue mapping module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-23 00:12:22 -07:00
Alex Forencich
d45857fb98 fpga/app/dma_bench: Add DMA benchmark application 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-21 14:19:43 -07:00
Alex Forencich
6044b75fa3 fpga/app/template: Add extension kernel module for template application 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-21 13:43:36 -07:00
Alex Forencich
e2cf0947ae fpga/app/template: Add utility for template application 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-21 13:42:56 -07:00
Alex Forencich
7f8bbe30de Add application ID 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-21 13:15:45 -07:00
Alex Forencich
ba70498518 fpga: Add DMA immediate connections and parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-20 15:00:58 -07:00
Alex Forencich
f082196b4a Expose EVENT_QUEUE_INDEX_WIDTH parameter at top-level 2022-03-29 23:15:06 -07:00
Alex Forencich
4310c3e0e7 Pass SCHED_PER_IF and PTP_PORT_CDC_PIPELINE parameters through to application block 2022-03-28 21:57:53 -07:00
Alex Forencich
cbd9d0dfc6 Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports 2022-03-28 17:23:27 -07:00
Alex Forencich
09128df360 Add SCHED_PER_IF parameter to split scheduler count from port count 2022-03-28 15:20:33 -07:00
Alex Forencich
dfae34ed25 Pass through PTP pipelining settings 2022-03-28 00:50:29 -07:00
Alex Forencich
8fc832bbd2 Parametrization update 2022-03-04 15:37:49 -08:00
Alex Forencich
2909d205de Remove unused files 2022-02-16 17:40:28 -08:00
Alex Forencich
3997e0d95b Parametriztion updates, add RAM_ADDR_WIDTH as a top-level parameter 2022-02-15 18:01:43 -08:00
Alex Forencich
627ac359d5 Add layer 2 ingress/egress modules 2022-02-13 23:09:41 -08:00
Alex Forencich
b7bc240aa6 Add JTAG and GPIO passthroughs to application section 2022-01-27 23:06:05 -08:00
Alex Forencich
335a5e890b Initial implementation of shared interface datapath 2021-12-31 14:33:31 -08:00
Alex Forencich
ce21774f06 Register space reorganization 2021-12-29 22:31:46 -08:00
Alex Forencich
7a43618e3c Use start_soon instead of fork 2021-12-10 20:43:21 -08:00
Alex Forencich
8674bd1e69 Update app testbench 2021-11-30 15:36:38 -08:00
Alex Forencich
8f887005e5 Update Ethernet interface configuration detection in testbenches 2021-11-22 17:04:50 -08:00
Alex Forencich
74f4c6fc2d Support using separate clock for PTP timestamps on RX path 2021-11-18 23:56:51 -08:00
Alex Forencich
5bf9de656c Update testbenches 2021-11-17 18:08:40 -08:00
Alex Forencich
7ac4797336 Add default_nettype none and resetall directives 2021-10-20 21:53:39 -07:00
Alex Forencich
d24c53a2ad Add application section 2021-09-09 16:01:26 -07:00