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Author SHA1 Message Date
Alex Forencich
f687aba432 fpga/mqnic: Update designs to use port mapping modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-13 01:37:10 -07:00
Alex Forencich
c587bc54a1 fpga/common: Add port mapping modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-12 21:16:17 -07:00
Alex Forencich
3d5dc74e01 fpga/common: Fix MTU register write addresses 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-12 14:10:47 -07:00
Alex Forencich
57905a5ef9 fpga/mqnic/ZCU106/fpga_zynqmp: Rewrite zynq PS TCL script, rework PS clock settings, switch to 300 MHz PL clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-11 12:25:51 -07:00
Alex Forencich
e9b62594c0 modules/mqnic: Fix typo in reading nominal clock period registers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-11 10:55:07 -07:00
Alex Forencich
72d8583235 fpga/mqnic/ZCU106/fpga_zynqmp: Remove unused I2C interface 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-11 10:54:58 -07:00
Alex Forencich
1d9c63ec66 docs: Update device lists 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-09 23:04:16 -07:00
Alex Forencich
4b4922c858 fpga/mqnic: Add 10G mqnic design for DNPCIe_40G_KU_LL_2QSFP 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-09 23:03:31 -07:00
Alex Forencich
c5d5fe8a64 fpga/mqnic: Remove unused wires 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-09 23:02:44 -07:00
Alex Forencich
1797fdecec docs: Fix table 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-07 22:42:47 -07:00
Alex Forencich
59e4c73252 docs: Add SoC section to device list 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-07 22:41:43 -07:00
Alex Forencich
1bb7053a68 ZCU106/fpga_zynqmp: Add integration test 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-07 21:42:01 -07:00
Alex Forencich
5f7c051b5b ZCU106/fpga_zynqmp: Sync module parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-07 21:41:06 -07:00
Alex Forencich
2eb4e5c4bd ZCU106/fpga_zynqmp/ps/petalinux/: Enable PTP in kernel and add linuxptp package 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-07 19:23:36 -07:00
Joachim Foerster
4250bde2a3 docs/source/: Add section about PetaLinux tools 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-04-07 18:41:05 +02:00
Joachim Foerster
eb17563097 ZCU106/fpga_zynqmp/ps/petalinux/: Add shortcut Makefile target "build-boot" to build PetaLinux including boot files in one step 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-04-07 18:41:05 +02:00
Joachim Foerster
2252308dc2 ZCU106/fpga_zynqmp/: README: Provide more information on how to build and test 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-04-07 18:41:05 +02:00
Joachim Foerster
1191908e68 ZCU106/fpga_zynqmp/ps/petalinux/: rootfs: Enable and include layer meta-corundum and its recipes 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-04-07 18:41:05 +02:00
Joachim Foerster
442a24c5a7 ZCU106/fpga_zynqmp/ps/petalinux/: rootfs: Include various kernel module and network device tools 
- kmod (for modinfo)
- ethtool
- net-tools (for arp)
- iputils-ping (for ping; Busybox' ping does not support flood ping option)
- iproute2 (for ip; Busybox' ip is very limited)
- tcpdump
- iperf2

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
 2022-04-07 18:41:05 +02:00
Joachim Foerster
5700aba9a0 ZCU106/fpga_zynqmp/ps/petalinux/: dts: Add custom device tree node for mqnic device 
Currently consists of 4 parts:
- Removing stub nodes generated by Xilinx device tree generator.
- Adding a custom, manually edited node (needs manual adjustment in case PS
  settings are changed!)
  NOTE: In the future this node might be reduced or removed all together after
  having added a plugin for Xilinx' device tree generator
  (https://github.com/Xilinx/device-tree-xlnx.git), which properly automatically
  generates such a node.
- Adding eeprom nodes for the SFP module I2C buses.
- Disabling the node for the USER MGT SI570 (U56) chip to make Linux NOT touch
  this chip on startup. See lengthy comment.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
 2022-04-07 18:41:05 +02:00
Joachim Foerster
2dbea0f913 ZCU106/fpga_zynqmp/ps/petalinux/: Add basic PetaLinux v2021.1 project 
- modify .gitignore compared to generated version by petalinux-create;
  to avoid committing unnecessary files (binaries, toolchain leftovers, ...)
- set machine name to "zcu106-reva"
- disable "copy to tftpboot directory"
- enable FSBL detailed debug output

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-04-07 17:14:57 +02:00
Joachim Foerster
e98b605a3f added psmake as a subproject 2022-04-07 17:14:32 +02:00
Joachim Foerster
ce464d780e Squashed 'fpga/lib/psmake/' content from commit 859b30a0 
git-subtree-dir: fpga/lib/psmake
git-subtree-split: 859b30a0ce0aa086d474b7b370e7369b807f03c9
 2022-04-07 17:14:32 +02:00
Joachim Foerster
b08a4404d4 fpga/lib: Add subtree manager for psmake 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-04-07 17:14:25 +02:00
Joachim Foerster
5730988c79 meta-corundum/: Add PetaLinux/Yocto meta layer, include recipe for mqnic kernel module and support tools 
For now, this layer is marked compatible with the Yocto version which PetaLinux
v2021.1 is based on (codename "gatesgarth"), only. Other version might be added
as needed (space separated). Incompatibilities with older versions are not known
at this point in time.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-04-07 17:14:25 +02:00
Joachim Foerster
26c70bbb8a modules/mqnic/: Add platform driver support 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-04-07 17:14:25 +02:00
Alex Forencich
984aefe508 Fix tag indexing 2022-04-06 13:24:05 -07:00
Alex Forencich
89db2a29b7 When EXTEND_RAM_SEL is not set, do not modify ram_sel 2022-04-06 13:23:46 -07:00
Alex Forencich
32b4f2cb1f Improve block operation tests 2022-04-04 15:21:25 -07:00
Alex Forencich
43719a9f73 Cleanup 2022-04-04 15:05:46 -07:00
Alex Forencich
e7a83364d0 Update testbenches 2022-04-04 15:05:21 -07:00
Alex Forencich
389911e126 Update example design to test immediate write 2022-04-04 15:04:57 -07:00
Alex Forencich
a5dcb3d27c Add support for writing immediate data to DMA IF modules 2022-04-04 12:40:42 -07:00
Alex Forencich
34fe24287d Simplify logic 2022-04-01 01:42:25 -07:00
Alex Forencich
7fcec10961 Add internal RAM_DATA_WIDTH parameter 2022-04-01 01:11:30 -07:00
Alex Forencich
1f46987ed8 Fix typo in Stratix 10 shim 2022-03-31 23:19:50 -07:00
Alex Forencich
4bbd187567 Add statistics outputs to AXI DMA IF modules 2022-03-31 17:56:05 -07:00
Alex Forencich
dd7cc63d55 Correct reporting of request length statistics for zero-length operations in PCIe DMA IF modules 2022-03-31 17:04:03 -07:00
Alex Forencich
2aeb820d35 Add operation table size assertion in AXI DMA IF modules 2022-03-31 16:42:46 -07:00
Joachim Foerster
80d5bda23f ZCU106/fpga_zynqmp: Fix maximum burst length for AXI Master 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-03-31 17:24:16 +02:00
Joachim Foerster
62879ff3ea ZCU106/fpga_zynqmp: Support parameter EVENT_QUEUE_INDEX_WIDTH, reduce Events queues to number of CPU cores 
- Keep parameter defaults in Verilog file at global of 32, though
- Select 4 Event queues via config.tcl, only

Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-03-31 17:24:16 +02:00
Andreas Braun
dc77c9e92a ZCU106/fpga_zynqmp: Reduce number of IRQs to number of CPU cores 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
 2022-03-31 17:22:27 +02:00
Andreas Braun
dce11522fa ZCU106/fpga_zynqmp: Reduce number of RX/TX queues to 32 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-03-31 17:22:27 +02:00
Andreas Braun
35517037e6 ZCU106/: Add design based on ZynqMP PS as host system, Vivado v2021.1 
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
Signed-off-by: Joachim Förster <joachim.foerster@missinglinkelectronics.com>
 2022-03-31 17:22:27 +02:00
Alex Forencich
ac5f942128 Support error reporting in AXI DMA interface modules 2022-03-31 01:48:36 -07:00
Alex Forencich
0b9c7671fb Minor refactor of zero-length handling logic 2022-03-31 00:05:55 -07:00
Alex Forencich
7cae50fa10 Support zero-length operations in AXI DMA interface modules 2022-03-30 23:40:02 -07:00
Alex Forencich
3f967c673f Read zero length flag on all paths 2022-03-30 23:39:34 -07:00
Alex Forencich
b7aa4f77d7 merged changes in eth 2022-03-30 16:32:56 -07:00
Alex Forencich
84004c720d merged changes in axis 2022-03-30 16:03:34 -07:00