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Author SHA1 Message Date
Alex Forencich
2e3b15239b Update Vivado IP 2017-05-18 13:49:10 -07:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
6c37731841 merged changes in axis 2017-05-18 13:36:02 -07:00
Alex Forencich
3b0cfbbfed Use extend instead of for loop 2017-05-18 13:35:42 -07:00
Alex Forencich
aebe0549dd Happy new year 2017-05-18 13:35:11 -07:00
Alex Forencich
c2e459c971 Connect transceiver control lines 2017-03-09 17:14:14 -08:00
Alex Forencich
3b47b422fa Fix Vivado clock groups 2016-10-06 17:52:23 -07:00
Alex Forencich
77ecbd7dcb Makefile updates 2016-10-05 17:41:00 -07:00
Alex Forencich
d5928ee776 Trim UDP and IP payloads to proper length 2016-10-05 17:33:05 -07:00
Alex Forencich
270641b7a3 Update UDP modules and example designs to utilize UDP checksum modules 2016-09-30 22:15:21 -07:00
Alex Forencich
4e522e52af Clean up endpoint modules 2016-09-30 22:02:29 -07:00
Alex Forencich
0b6614e8d4 Add UDP checksum generator modules and testbenches 2016-09-30 21:59:04 -07:00
Alex Forencich
15330486e8 Convert GMII and RGMII shims to use generic IO components 2016-09-29 20:10:10 -07:00
Alex Forencich
d13abd76c4 Add generic IO components 2016-09-29 20:07:29 -07:00
Alex Forencich
88150c9d5f Update and rework endpoints, update testbenches 2016-09-13 15:24:02 -07:00
Alex Forencich
64354e0b60 merged changes in axis 2016-09-12 14:08:45 -07:00
Alex Forencich
5fa36eeaa7 Rework endpoints, update testbenches 2016-09-12 13:38:34 -07:00
Alex Forencich
0691c9d61b Fix output pipeline issue 2016-09-02 10:43:21 -07:00
Alex Forencich
306c0ea590 Rework mux logic 2016-08-29 19:25:43 -07:00
Alex Forencich
86ffbd98e8 merged changes in axis 2016-08-28 14:13:55 -07:00
Alex Forencich
4245e2bf00 Rework mux logic 2016-08-24 16:53:13 -07:00
Alex Forencich
3207a2b7d2 Remove redundant code 2016-08-23 09:25:19 -07:00
Alex Forencich
bd0d05411b merged changes in axis 2016-08-22 08:56:24 -07:00
Alex Forencich
e989f15ff4 Remove some test cases 2016-08-22 08:17:26 -07:00
Alex Forencich
24f7aee8b2 Add COBS encoder and decoder modules and testbench 2016-08-21 20:03:54 -07:00
Alex Forencich
c4b75e65a3 merged changes in axis 2016-08-04 18:05:47 -07:00
Alex Forencich
e6d78b7ca7 Add extra testbench delay 2016-08-04 18:03:24 -07:00
Alex Forencich
a961a9756a Add FIFO output pipeline registers to aid block RAM output timing closure 2016-08-04 18:03:00 -07:00
Alex Forencich
36af29db77 Add i2c init code for si570 reference oscillator 2016-08-03 14:44:10 -04:00
Alex Forencich
833d1dac81 Route 10G link status to LEDs 2016-07-28 09:57:36 -04:00
Alex Forencich
2365f4b6fc Connect QSFP module control pins 2016-07-28 09:56:13 -04:00
Alex Forencich
70912e8255 merged changes in axis 2016-07-27 13:44:39 -07:00
Alex Forencich
b44e401b95 Update async FIFO resets 2016-07-27 13:42:44 -07:00
Alex Forencich
795ae8a4db Add 10G example design for VCU108 board 2016-07-26 14:14:16 -04:00
Alex Forencich
2f94c92e8c Merge branch 'master' of github.com:alexforencich/verilog-ethernet 2016-07-25 16:21:12 -04:00
Alex Forencich
7d7ddd0d98 merged changes in axis 2016-07-25 13:17:41 -07:00
Alex Forencich
c27e74c7d4 Update readme 2016-07-25 13:15:59 -07:00
Alex Forencich
06bfa1944c Add AXI stream switch module, generator script, and testbench 2016-07-25 13:12:10 -07:00
Alex Forencich
5fe35a79d2 Add tdest support to axis_ep 2016-07-25 11:28:35 -07:00
Alex Forencich
d023213fda Support generating asymmetric crosspoints 2016-07-24 13:06:59 -07:00
Alex Forencich
52fc34d82e Assume first tkeep bit is always set 2016-07-20 12:36:59 -07:00
Alex Forencich
c34a9c2197 Add 32 bit XGMII support 2016-07-19 19:59:47 -07:00
Alex Forencich
7d7cba0838 Add bus width checks 2016-07-19 16:21:15 -07:00
Alex Forencich
e38ffe16b8 Adjust config vector assignment 2016-07-13 14:38:22 -04:00
Alex Forencich
018b3b2691 Fix signal width 2016-07-13 12:21:37 -04:00
Alex Forencich
61d41789d7 Remove unused parameter; update XDC file 2016-07-13 11:57:14 -04:00
Alex Forencich
5afe1d7e1e Add example design for VCU108 board 2016-07-05 11:52:28 -04:00
Alex Forencich
1f52bf826d Update vivado.mk 2016-07-05 11:17:16 -04:00
Alex Forencich
cbf1df718a Add example design for Digilent Nexys Video board 2016-06-29 12:00:05 -07:00
Alex Forencich
a430e4463e Add RGMII endpoint and PHY interface module 2016-06-29 06:13:46 -07:00