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917 Commits

Author SHA1 Message Date
Alex Forencich
db621ffa7d Use CMAC wrapper in 100G mqnic design for 250-SoC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 18:01:43 -08:00
Alex Forencich
cdda035427 Use CMAC wrapper in 100G mqnic design for VCU1525 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 17:35:09 -08:00
Alex Forencich
e51e5a84af Use CMAC wrapper in 100G mqnic design for Alveo U50 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 17:07:12 -08:00
Alex Forencich
39c5744e99 Use CMAC wrapper in 100G mqnic design for Alveo U280 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 16:30:55 -08:00
Alex Forencich
3d993e4479 Use CMAC wrapper in 100G mqnic design for Alveo U250 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 16:00:45 -08:00
Alex Forencich
f67bd98719 Use CMAC wrapper in 100G mqnic design for Alveo U200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 12:38:14 -08:00
Alex Forencich
49be896333 Use CMAC wrapper in 100G mqnic design for ADM-PCIE-9V3 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 11:49:34 -08:00
Alex Forencich
f70f4d9b90 Use CMAC wrapper in 100G mqnic design for fb2CG@KU15P 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 11:42:07 -08:00
Alex Forencich
bf7cf3fef9 Add CMAC wrapper 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-09 20:58:30 -08:00
Alex Forencich
f6262c3606 fpga/mqnic: Update FIFO parameter naming 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 23:57:50 -07:00
Alex Forencich
0cb106e2aa merged changes in eth 2022-11-01 23:57:35 -07:00
Alex Forencich
8c733dff9e fpga/mqnic/fb2CG: Update placement constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-17 13:01:16 -07:00
Alex Forencich
e3f2d8990d fpga/mqnic: Use all ports for TDMA designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 23:30:54 -07:00
Alex Forencich
b19ff209da fpga/common: More parameter cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 23:30:17 -07:00
Alex Forencich
d3942da875 fpga: Add clock info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 19:45:02 -07:00
Alex Forencich
6fa30bc94c fpga/mqnic: Fix critical warnings when MIGs are not present 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 13:47:41 -07:00
Alex Forencich
d0cc106783 fpga: Remove redundant RX_RSS_ENABLE parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-13 17:10:25 -07:00
Alex Forencich
2714ba5cdd merged changes in pcie 2022-10-12 23:57:47 -07:00
Alex Forencich
01df80df86 fpga/mqnic: Disable MIGs by default 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 23:57:27 -07:00
Alex Forencich
5e52a52f5e fpga/mqnic: Add MIGs and HBM controllers for most boards 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 19:00:49 -07:00
Alex Forencich
941288e926 fpga/common: Add AXI interfaces for DDR and HBM to core logic and application section 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 17:12:23 -07:00
Alex Forencich
eb990643f2 fpga/mqnic: various minor cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 17:12:07 -07:00
Alex Forencich
5f1e74b0e1 Add PROJECT variable, remove multiple stem matches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 13:33:09 -07:00
Alex Forencich
7017e7d49b Explicitly set top module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 12:29:01 -07:00
Alex Forencich
ceb6a9ca06 Update clean target 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 12:26:39 -07:00
Alex Forencich
9c98f12392 Write debug probes file alongside bit file 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-10 23:37:54 -07:00
Alex Forencich
9628401780 Normalize output file location 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-10 21:47:53 -07:00
Alex Forencich
caf2a0993b fpga: Output hierarchical utilization reports 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-06 21:17:25 -07:00
Alex Forencich
fe37e4a4bb fpga/common: Use correct parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-06 21:15:26 -07:00
Alex Forencich
56fe10f27d fpga/common: Fix lost TX request status issue in transmit engine 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-21 15:20:27 -07:00
Alex Forencich
efbeecde35 fpga/common: Clean up parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-21 15:19:49 -07:00
Alex Forencich
ebbddb5559 fpga/common: Add multiple queue test to core testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-20 21:59:02 -07:00
Alex Forencich
4b8aaea5c1 fpga/common: Add skid buffer to TX/RX engine DMA descriptor outputs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-20 21:50:58 -07:00
Alex Forencich
d7904b8007 fpga: Add support for IRQ rate limiting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 15:24:40 -07:00
Alex Forencich
2a69e07acb merged changes in pcie 2022-09-04 12:03:44 -07:00
Alex Forencich
1486da601f fpga: Add clock period parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 12:03:35 -07:00
Alex Forencich
803841421e fpga/common: Fix tied-off net name 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-03 18:34:42 -07:00
Alex Forencich
44c81574d7 fpga/common: Add backpressure to completion queue manager event/interrupt output 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-16 18:51:53 -07:00
Alex Forencich
647a168299 Enable more peripherals in Zynq designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-16 18:49:02 -07:00
Alex Forencich
1b9f5d1032 fpga/mqnic/ZCU102: Add 10G mqnic design for ZCU102 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-16 01:44:52 -07:00
Alex Forencich
171c2a9a69 fpga/mqnic/ZCU106/fpga_zynqmp: Remove SI570 workaround 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-15 23:54:02 -07:00
Alex Forencich
338457cd75 merged changes in pcie 2022-08-15 23:47:49 -07:00
Alex Forencich
1c1db788ac fpga/common: Fix incorrect parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-08 13:10:05 -07:00
Alex Forencich
d0ce01de7f fpga/mqnic/S10DX_DK: fix typo 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-05 16:28:15 -07:00
Alex Forencich
6c6648f114 fpga/mqnic: Add RAM inference directive to Intel designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-05 16:27:29 -07:00
Alex Forencich
f3bf63a775 merged changes in pcie 2022-08-05 16:25:42 -07:00
Alex Forencich
0c877a45fb fpga/build_images.py: update quartus message parsing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-04 13:40:34 -07:00
Alex Forencich
d6186eff88 fpga/build_images.py: process both stdout and stderr 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-04 13:40:09 -07:00
Alex Forencich
cc99484d99 fpga/common: add missing parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 23:04:23 -07:00
Alex Forencich
81648cf85b fpga/mqnic: Clean up PCIe DMA IF flow control connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 23:04:05 -07:00