10 Commits

Author	SHA1	Message	Date
Alex Forencich	c62df81292	Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH	2022-02-15 00:39:46 -08:00
Alex Forencich	d2c72d3583	Add attributes to RAMs for proper synthesis in Quartus	2021-11-02 22:28:05 -07:00
Alex Forencich	90959b8795	Add default_nettype none and resetall directives	2021-10-20 17:49:30 -07:00
Alex Forencich	36ec7aaa16	Add error reporting to DMA modules	2021-08-02 17:24:00 -07:00
Alex Forencich	9c8417799d	Add output FIFO and write done tracking to AXI stream sink DMA client	2021-02-24 13:48:56 -08:00
Alex Forencich	070689692d	Add wr_done signal to RAM model and placeholders to DMA components	2021-02-24 13:47:53 -08:00
Alex Forencich	057a93e07a	Sync data handling	2021-02-16 13:56:44 -08:00
Alex Forencich	1e75c3cc70	Fix AXI stream DMA client bug causing dropped writes when widths are the same	2020-08-06 21:32:10 -07:00
Alex Forencich	0d4e9989c8	Fix asserts	2020-08-06 21:31:58 -07:00
Alex Forencich	e1035ed57d	Add AXI stream sink DMA client module and testbench	2019-10-12 22:35:57 -07:00