37 Commits

Author	SHA1	Message	Date
Alex Forencich	306aa4db0b	Update VCU118 XDC	2020-10-06 00:39:32 -07:00
Alex Forencich	6aba3a741a	Update makefiles	2020-08-06 17:19:11 -07:00
Alex Forencich	fd908dd2aa	Clean up clock connections	2020-08-06 17:15:38 -07:00
Alex Forencich	b7c089dd22	XDC clean up	2020-07-13 23:58:30 -07:00
Alex Forencich	a27c04a949	Convert to TCL IP	2020-07-01 19:43:26 -07:00
Alex Forencich	27ed447005	Use common sync_reset module files	2020-03-27 18:27:45 -07:00
Alex Forencich	a55c354924	Parametrize Ethernet frame parsing	2020-02-21 21:37:57 -08:00
Alex Forencich	4ac6d6803b	Parametrize ARP components	2020-02-20 16:49:47 -08:00
Alex Forencich	c5e886769a	Fix typo	2019-07-19 10:29:55 -07:00
Alex Forencich	16e5ec2106	Update example designs	2019-07-18 17:13:47 -07:00
Alex Forencich	e5171d8749	Enable flash programming in VCU118 example designs	2019-07-01 17:51:31 -07:00
Alex Forencich	dfafa9c83d	Update vivado.mk	2019-06-27 00:59:36 -07:00
Alex Forencich	025f05e667	Add nojournal and nolog	2019-06-27 00:48:20 -07:00
Alex Forencich	7cce7896b5	Update programming commands	2019-06-25 23:46:44 -07:00
Alex Forencich	0927f4c326	Fix readme	2019-06-19 23:51:04 -07:00
Alex Forencich	1eb9c39ed3	Add VCU118 25G example design	2019-06-19 23:25:06 -07:00
Alex Forencich	a031993b26	Update example designs	2019-06-19 23:16:57 -07:00
Alex Forencich	249f9d9df4	Update example designs	2019-05-10 22:55:44 -07:00
Alex Forencich	5428d81fd6	Update AXI stream switch instances	2019-03-28 23:56:06 -07:00
Alex Forencich	0ca8c9a59b	Update example design timing constraints	2019-03-28 17:59:30 -07:00
Alex Forencich	e120a85607	Use correct clock	2019-03-28 17:56:55 -07:00
Alex Forencich	d16d291d5e	Upgrade example design IP cores	2019-03-28 16:30:34 -07:00
Alex Forencich	cd6b87e984	Enable bitstream compression in example designs	2019-02-06 21:25:30 -08:00
Alex Forencich	52058cb5de	Swap out PHY in VCU118 example design	2019-02-05 18:28:42 -08:00
Alex Forencich	e882ed143f	Update example designs	2018-11-08 09:20:33 -08:00
Alex Forencich	0a6bee6d69	Update example designs	2018-11-08 09:17:29 -08:00
Alex Forencich	7d6889add6	Update example designs	2018-10-30 21:32:32 -07:00
Alex Forencich	00dc50826d	Update example designs	2018-10-24 01:03:44 -07:00
Alex Forencich	030fe90bf5	Fix example design testbench	2018-10-19 15:33:25 -07:00
Alex Forencich	8982b4f4e1	Fix modsell pin	2018-06-29 13:00:41 -07:00
Alex Forencich	cd51821bf7	Add parameters	2018-06-22 18:56:05 -07:00
Alex Forencich	6368529b6f	Add clock frequency annotation	2018-06-14 13:42:10 -07:00
Alex Forencich	e4672915e6	Update testbenches to use instances()	2018-06-13 22:43:11 -07:00
Alex Forencich	298ae4defa	Update MAC module instantiation	2018-06-13 22:16:02 -07:00
Alex Forencich	8e1f14e9a7	Add VCU118 10G example design	2018-06-13 19:30:07 -07:00
Alex Forencich	05c6743473	Update xdc	2018-06-13 19:18:59 -07:00
Alex Forencich	f4d7edf23f	Add VCU118 example design	2018-06-13 14:33:07 -07:00