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Author SHA1 Message Date
Alex Forencich
3138795899 Fix rate limiter testbenches 2015-03-21 02:55:30 -07:00
Alex Forencich
6e2eda256d Improve frame drop logic in frame FIFOs, add DROP_WHEN_FULL option to disable input tready signal 2015-02-28 19:32:08 -08:00
Alex Forencich
8582ab0749 Update readme 2014-12-03 19:00:12 -08:00
Alex Forencich
3c7e3b0424 Add SRL register module and testbench 2014-12-03 18:51:46 -08:00
Alex Forencich
10fd51f192 Add SRL FIFO module and testbench 2014-12-03 18:49:33 -08:00
Alex Forencich
385e358c08 Use non-broken myhdl 2014-12-03 18:02:53 -08:00
Alex Forencich
b83dd34185 Fix register names 2014-12-03 13:15:13 -08:00
Alex Forencich
fbcbbe3a69 Remove adder tree 2014-11-21 10:43:20 -08:00
Alex Forencich
63f6e96492 Add tuser signal to crosspoint module 2014-11-21 01:07:02 -08:00
Alex Forencich
27cb9609f1 clog2 does not work in localparam in XST 2014-11-21 01:06:24 -08:00
Alex Forencich
b07c2d63b0 Parametrize tag and counter widths 2014-11-19 23:06:43 -08:00
Alex Forencich
0c3af7d5bb Reverse priority in arbitrated mux 2014-11-16 02:00:27 -08:00
Alex Forencich
d193ca5905 Add LSB_PRIORITY parameter 2014-11-16 01:58:17 -08:00
Alex Forencich
b123525597 Add enable signal 2014-11-16 01:38:20 -08:00
Alex Forencich
7c86999399 Minor reorganization 2014-11-13 16:26:07 -08:00
Alex Forencich
789c7da6d6 Fix parameter 2014-11-13 10:39:41 -08:00
Alex Forencich
698234c297 Update comments 2014-11-13 10:39:27 -08:00
Alex Forencich
8a46e6900c Update readme 2014-11-13 10:21:54 -08:00
Alex Forencich
bd90208153 Update readme 2014-11-13 10:19:46 -08:00
Alex Forencich
851aeb9309 Fix block parameter 2014-11-13 10:06:28 -08:00
Alex Forencich
5f0d23a3ad Add AXI arbitrated mux module and testbench 2014-11-13 02:01:45 -08:00
Alex Forencich
a8970e6e75 Change block parameter 2014-11-13 02:01:07 -08:00
Alex Forencich
a1633f27d8 Add arbiter module 2014-11-13 01:22:59 -08:00
Alex Forencich
3399f284b2 Add priority encoder 2014-11-12 23:59:02 -08:00
Alex Forencich
5c49ed6191 Add AXI stream demux and testbench 2014-11-12 19:21:28 -08:00
Alex Forencich
73a580df95 Update readme 2014-11-12 15:53:47 -08:00
Alex Forencich
5af6dc3501 Add AXI stream mux and testbench 2014-11-12 15:49:07 -08:00
Alex Forencich
aafacb372e Trim trailing spaces 2014-11-12 15:32:05 -08:00
Alex Forencich
3816eb3c20 Fix parameters 2014-11-12 02:06:18 -08:00
Alex Forencich
d6784d189d Update readme 2014-11-12 02:03:59 -08:00
Alex Forencich
a28a534bff Add AXI stream crosspoint module and testbench 2014-11-12 01:54:31 -08:00
Alex Forencich
7804272b2e Updated readme 2014-11-09 02:13:20 -08:00
Alex Forencich
10e0d7d1bb Add AXI async frame fifo and testbench 2014-11-08 21:29:39 -08:00
Alex Forencich
6fa46b6c57 Add AXI frame fifo and testbench 2014-11-08 21:07:47 -08:00
Alex Forencich
b232a6459d Remove counter from AXI fifo modules 2014-11-08 12:45:36 -08:00
Alex Forencich
918ef8f76c Add AXI async FIFO and testbench 2014-11-08 00:23:23 -08:00
Alex Forencich
ac2f7e546d Adjust syntax for old Python 2 2014-11-05 16:40:27 -08:00
Alex Forencich
e8c43653e3 Adjust syntax for old Python 2 2014-11-05 16:33:33 -08:00
Alex Forencich
849f3c174a Add .travis.yml 2014-11-05 16:22:09 -08:00
Alex Forencich
0507fd4ca9 Update readme 2014-11-05 16:19:00 -08:00
Alex Forencich
af0dce33b1 Separate out input mux in AXI frame joiner 2014-10-28 01:55:42 -07:00
Alex Forencich
f827b5eafb Improve output register filling 2014-10-22 15:13:42 -07:00
Alex Forencich
5f14df216a Improve output register filling 2014-10-22 15:11:41 -07:00
Alex Forencich
a2a509884e Improve output register filling 2014-10-22 15:10:21 -07:00
Alex Forencich
47a8c35d5d Improve output register filling 2014-10-22 15:10:07 -07:00
Alex Forencich
a92eb4e57f Improve output register filling 2014-10-22 15:09:48 -07:00
Alex Forencich
7c3adb6c2b Add AXI stream frame joiner, generator, and testbench 2014-10-22 10:47:03 -07:00
Alex Forencich
3b1655f81f Update rate limit test bench to check more settings and verify rate 2014-10-21 23:25:28 -07:00
Alex Forencich
67bb09ba42 Add busy output to statistics collection module 2014-10-21 16:09:55 -07:00
Alex Forencich
f22381baa2 Initial commit of basic statistics collection module 2014-10-21 13:20:37 -07:00