19 Commits

Author	SHA1	Message	Date
Alex Forencich	b9e0af3634	Revert change to early ready conditions for improved throughput ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-09-18 12:07:11 -07:00
Alex Forencich	6d4458e5cc	Rewrite early ready condition ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-05-15 17:36:00 -07:00
Alex Forencich	268d0c66b8	Rewrite resets ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-05-13 12:57:41 -07:00
Alex Forencich	073d50d9dc	Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8	2022-03-30 16:02:17 -07:00
Alex Forencich	2972a1fa81	Add default_nettype none and resetall directives	2021-10-20 15:33:38 -07:00
Alex Forencich	c5f44c70d1	Add parameter documentation	2019-07-24 13:54:21 -07:00
Alex Forencich	6f4ab8f180	Rename ports	2018-10-25 11:59:13 -07:00
Alex Forencich	5df7efe516	Happy new year	2018-02-26 12:25:20 -08:00
Alex Forencich	b00eaf4d3c	Add tkeep signal and update testbench for stat counter	2017-11-21 00:17:42 -08:00
Alex Forencich	aebe0549dd	Happy new year	2017-05-18 13:35:11 -07:00
Alex Forencich	be4034071b	Happy new year	2016-01-05 00:24:20 -08:00
Alex Forencich	0d22a35bd8	Update output registers, remove extraneous resets, fix constant widths	2015-11-08 23:05:38 -08:00
Alex Forencich	ca11618e6d	Convert to synchronous resets	2015-10-08 11:26:32 -07:00
Alex Forencich	b83dd34185	Fix register names	2014-12-03 13:15:13 -08:00
Alex Forencich	fbcbbe3a69	Remove adder tree	2014-11-21 10:43:20 -08:00
Alex Forencich	b07c2d63b0	Parametrize tag and counter widths	2014-11-19 23:06:43 -08:00
Alex Forencich	47a8c35d5d	Improve output register filling	2014-10-22 15:10:07 -07:00
Alex Forencich	67bb09ba42	Add busy output to statistics collection module	2014-10-21 16:09:55 -07:00
Alex Forencich	f22381baa2	Initial commit of basic statistics collection module	2014-10-21 13:20:37 -07:00