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Author SHA1 Message Date
Alex Forencich
32abea89fa Update testbenches 2021-03-06 20:30:25 -08:00
Alex Forencich
c620cd23e7 merged changes in pcie 2021-03-06 20:29:02 -08:00
Alex Forencich
48e1c39e3f merged changes in eth 2021-03-06 20:27:23 -08:00
Alex Forencich
cd8566a6bc merged changes in axi 2021-03-06 20:27:13 -08:00
Alex Forencich
bdfeaa84ca Update testbenches 2021-03-06 20:06:23 -08:00
Alex Forencich
4af058fbdc Update testbenches 2021-03-06 20:04:19 -08:00
Alex Forencich
be689ebb77 Update testbenches 2021-03-06 19:55:50 -08:00
Alex Forencich
22b3bacf51 Update attribute name 2021-03-05 23:03:41 -08:00
Alex Forencich
d416e9f7fa Roll back PCIe tag count to 64 2021-03-05 14:04:52 -08:00
Alex Forencich
ee3784ca6e Add driver support for Silicom Gecko BMC 2021-03-04 22:44:49 -08:00
Alex Forencich
d2fdf1a7bd Update mqnic-bmc to support Gecko BMC 2021-03-04 22:39:25 -08:00
Alex Forencich
705133bf7a Add SPI interface to Gecko BMC on fb2CG@KU15P 2021-03-04 22:34:52 -08:00
Alex Forencich
2cbdb40a4c Index instead of offset 2021-03-04 19:18:21 -08:00
Alex Forencich
3a503cc6aa Rename BMC-related methods 2021-03-04 19:02:59 -08:00
Alex Forencich
a644d6dd3f Update Vivado makefiles 2021-03-01 23:05:37 -08:00
Alex Forencich
d0b19efce5 Reconcile PCIe changes 2021-03-01 00:25:15 -08:00
Alex Forencich
421dbd5d0f merged changes in pcie 2021-03-01 00:03:44 -08:00
Alex Forencich
78d755ea9a Minor optimization 2021-02-28 22:31:29 -08:00
Alex Forencich
0c6bb169bc Rework FIFO distributed RAM init code 2021-02-28 22:18:54 -08:00
Alex Forencich
670dfa0d11 Fix pcie_us_axi_dma_wr testbench file list 2021-02-28 19:50:45 -08:00
Alex Forencich
5715e12d41 Remove tag manager module 2021-02-28 19:37:16 -08:00
Alex Forencich
266fed8d20 Update example design file list 2021-02-28 19:35:35 -08:00
Alex Forencich
438a4fdcc9 Use FIFOs for PCIe tag management in PCIe read DMA modules 2021-02-28 19:34:24 -08:00
Alex Forencich
a3f805a0c3 Add pipeline register 2021-02-28 11:34:29 -08:00
Alex Forencich
92951723aa Offset stored address by TLP byte length to eliminate updating stored address 2021-02-28 01:36:03 -08:00
Alex Forencich
603784b742 Fix operation init handling 2021-02-26 01:19:56 -08:00
Alex Forencich
912ef845a3 Rename tag to pcie_tag 2021-02-25 23:54:40 -08:00
Alex Forencich
062495b780 Remove redundant parameter PCIE_EXT_TAG_ENABLE 2021-02-25 18:20:08 -08:00
Alex Forencich
8294eecd65 Remove redundant parameter PCIE_TAG_WIDTH 2021-02-25 18:10:59 -08:00
Alex Forencich
8cfbe18335 Use FIFO for op tag management in PCIe read DMA modules 2021-02-25 16:30:23 -08:00
Alex Forencich
a3c104f7dd Connect write done signals 2021-02-24 15:07:26 -08:00
Alex Forencich
65fdc332b3 merged changes in pcie 2021-02-24 15:03:37 -08:00
Alex Forencich
365d39990d merged changes in eth 2021-02-24 15:03:24 -08:00
Alex Forencich
6bc757dbc0 merged changes in axi 2021-02-24 15:03:08 -08:00
Alex Forencich
41d0e7cb7e Minor optimization 2021-02-24 14:48:14 -08:00
Alex Forencich
63006e8092 Add output FIFO to DMA IF mux for read response data 2021-02-24 13:54:40 -08:00
Alex Forencich
ed29997a59 Add write done tracking to DMA IF mux 2021-02-24 13:51:50 -08:00
Alex Forencich
6fb2eb6b4e Remove unnecessary delays from testbenches 2021-02-24 13:50:45 -08:00
Alex Forencich
40a191a06d Add output FIFO and write done tracking to ultrascale PCIe read DMA interface 2021-02-24 13:50:05 -08:00
Alex Forencich
9c8417799d Add output FIFO and write done tracking to AXI stream sink DMA client 2021-02-24 13:48:56 -08:00
Alex Forencich
070689692d Add wr_done signal to RAM model and placeholders to DMA components 2021-02-24 13:47:53 -08:00
Alex Forencich
4b3d153cbd Add placement constraints for fb2CG@KU15P 2021-02-23 02:33:37 -08:00
Alex Forencich
2779087de9 Constrain DMA muxes to same SLR 2021-02-23 02:17:10 -08:00
Alex Forencich
ceebb9f20e Add more PCIe-related components to PCIe pblock 2021-02-23 00:55:05 -08:00
Alex Forencich
0afd441eba Fix active operation count logic 2021-02-17 21:14:51 -08:00
Alex Forencich
e5f5b1c352 Remove unused regs 2021-02-17 18:30:55 -08:00
Alex Forencich
68387161d4 Track active operation count to prevent status FIFO overflow 2021-02-17 18:29:44 -08:00
Alex Forencich
83b5d30347 Rewrite resets 2021-02-17 18:06:47 -08:00
Alex Forencich
057a93e07a Sync data handling 2021-02-16 13:56:44 -08:00
Alex Forencich
742ef1c272 Add same-width test cases to DMA clients 2021-02-16 01:26:05 -08:00