FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity
1,716 Commits 1 Branch 0 Tags
Commit Graph

1716 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Alex Forencich
7dba8c162c Add placement constraints for AU280 10G design 2021-01-13 21:09:25 -08:00
Alex Forencich
8f8fbf33a8 Update placement constraints for AU280 100G design 2021-01-13 20:56:18 -08:00
Alex Forencich
42e19e1e96 Add pipeline registers, floorplanning constraints for VCU118 100G design 2021-01-13 20:55:20 -08:00
Alex Forencich
240ce56ccf Add pipeline registers, floorplanning constraints for VCU1525 100G design 2021-01-13 20:54:42 -08:00
Alex Forencich
220511f661 Use little endian types in hardware structs 2021-01-13 20:19:45 -08:00
Alex Forencich
9ceacea0e0 Fix types 2021-01-13 20:18:01 -08:00
Alex Forencich
ddda63476c Make internal functions static 2021-01-13 20:09:09 -08:00
Alex Forencich
a91e2b7e17 Add KC705 SGMII example design 2020-12-30 17:15:34 -08:00
Alex Forencich
5a7fd98413 Add KC705 RGMII example design 2020-12-30 17:15:18 -08:00
Alex Forencich
8a021f5c9b Update KC705 XDC 2020-12-30 16:54:30 -08:00
Alex Forencich
22feb53e1d Update example design readmes 2020-12-30 16:48:37 -08:00
Alex Forencich
8e1ad2eba6 Add cocotb testbench for ptp_clock_cdc 2020-12-29 22:55:55 -08:00
Alex Forencich
7117de682a Add cocotb testbench for ptp_perout 2020-12-29 22:02:27 -08:00
Alex Forencich
0171afbb18 Add cocotb testbench for ptp_clock 2020-12-29 22:02:18 -08:00
Alex Forencich
e5bc5e1f49 Add cocotb testbench for arp_cache 2020-12-29 22:01:24 -08:00
Alex Forencich
25b890f8bb Remove extraneous code 2020-12-29 18:55:13 -08:00
Alex Forencich
c0c2f933c0 Rework sim_build output directory, fix default makefile target 2020-12-29 17:28:53 -08:00
Alex Forencich
87a6efe05c Rework sim_build output directory, fix default makefile target 2020-12-29 16:26:48 -08:00
Alex Forencich
03a78413c5 Rework sim_build output directory, fix default makefile target 2020-12-29 16:09:02 -08:00
Alex Forencich
77d22bfde0 Rework sim_build output directory, fix default makefile target 2020-12-29 14:47:12 -08:00
Alex Forencich
5a3d71823a Update readme 2020-12-28 20:44:00 -08:00
Alex Forencich
782d86a7d1 Remove readme link 2020-12-28 20:43:26 -08:00
Alex Forencich
731fd859ac Add Github Actions regression tests 2020-12-28 20:19:58 -08:00
Alex Forencich
4a98858bea Forward arguments to pytest 2020-12-28 20:19:46 -08:00
Alex Forencich
f47c529122 Add test durations 2020-12-28 19:33:56 -08:00
Alex Forencich
cd12721502 Add cococb testbenches for eth_axis_rx and eth_axis_tx 2020-12-28 19:28:38 -08:00
Alex Forencich
29dc7498d3 Add cocotb MAC testbenches 2020-12-28 19:26:46 -08:00
Alex Forencich
0359d8d76a Use absolute path to test directory 2020-12-28 19:25:59 -08:00
Alex Forencich
3a59569105 Remove extraneous import 2020-12-28 18:53:00 -08:00
Alex Forencich
db58c836f6 Use absolute path to test directory 2020-12-28 18:52:47 -08:00
Alex Forencich
a894af4815 Add tox.ini 2020-12-28 01:12:08 -08:00
Alex Forencich
079d6329cb Migrate example design testbenches to cocotb 2020-12-28 01:11:03 -08:00
Alex Forencich
4d31316fef Remove travis-ci 2020-12-25 02:09:50 -08:00
Alex Forencich
d1fc821c8b Fix simulation startup issue in rgmii_phy_if 2020-12-25 02:03:57 -08:00
Alex Forencich
a78627343d Change default target parameter 2020-12-25 01:48:24 -08:00
Alex Forencich
220e04d1a7 Update example design 2020-12-25 01:47:01 -08:00
Alex Forencich
2a2d8ac966 Fix reg type in VCU108 and VCU118 example designs 2020-12-20 14:22:52 -08:00
Alex Forencich
44bf507e24 Update readme 2020-12-19 14:59:02 -08:00
Alex Forencich
ba50df774d Add Github Actions regression tests 2020-12-19 14:18:05 -08:00
Alex Forencich
8d7f4b52bf Add test durations 2020-12-19 14:17:47 -08:00
Alex Forencich
0e0e9da047 Add tox.ini 2020-12-19 14:11:23 -08:00
Alex Forencich
a0a5ccc0a4 Add cocotb testbenches 2020-12-19 14:10:57 -08:00
Alex Forencich
7c19cb770d Properly name registers, CQ demux bug fix 2020-12-19 14:09:56 -08:00
Alex Forencich
cabad17552 Migrate example design testbenches to cocotb 2020-12-18 22:10:32 -08:00
Alex Forencich
99e91c4d90 Fix pointer handling issue in PCIe AXI DMA write module 2020-12-18 18:37:53 -08:00
Alex Forencich
0c0fdc479b Update testbenches for async send/recv 2020-12-18 17:40:36 -08:00
Alex Forencich
9ab1fb44b1 Convert send/recv to blocking 2020-12-18 16:50:50 -08:00
Alex Forencich
e3fb7d19b2 Fix PCIe config 2020-12-16 14:58:19 -08:00
Alex Forencich
ca7f0131ea Remove unnecessary __init__.py files 2020-12-15 18:59:49 -08:00
Alex Forencich
af07083b1f Update readme 2020-12-15 17:21:22 -08:00