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Author SHA1 Message Date
Alex Forencich
35ec697a6f Update readme 2020-07-13 13:41:33 -07:00
Alex Forencich
5dbb771958 Add AU280 AXI example design 2020-07-12 11:42:48 -07:00
Alex Forencich
fe729cdd86 Update readme 2020-07-12 11:34:31 -07:00
Alex Forencich
9b7fa688d5 Add 100G mqnic design for Alveo U280 2020-07-12 11:33:28 -07:00
Alex Forencich
6433275139 Add 10G mqnic design for Alveo U280 2020-07-12 11:33:18 -07:00
Alex Forencich
2d4c7925f0 Add Alveo board IDs 2020-07-11 23:07:50 -07:00
Alex Forencich
f99736d4f5 Convert to TCL IP 2020-07-11 20:07:13 -07:00
Alex Forencich
5dd5f8bb3e merged changes in pcie 2020-07-10 19:46:48 -07:00
Alex Forencich
7c10036183 merged changes in eth 2020-07-10 19:46:43 -07:00
Alex Forencich
0ff6282ed6 merged changes in axi 2020-07-10 19:46:37 -07:00
Alex Forencich
ce41b4c5ea Update readme 2020-07-10 16:07:31 -07:00
Alex Forencich
3898cf21ed Add DE2-115 example design 2020-07-10 15:38:43 -07:00
Alex Forencich
3b06f86dcf Add C10LP example design 2020-07-10 15:32:39 -07:00
Alex Forencich
59a51b4a9f Add SDC constraints for Quartus 2020-07-10 14:14:02 -07:00
Alex Forencich
65cb3cb441 merged changes in axis 2020-07-10 14:04:52 -07:00
Alex Forencich
71bd4a1811 Add SDC constraints for Quartus 2020-07-10 14:02:08 -07:00
Alex Forencich
ebae4e436d Update AXI simulation model 2020-07-02 21:28:35 -07:00
Alex Forencich
281e1a2156 Convert to TCL IP 2020-07-01 23:53:58 -07:00
Alex Forencich
a27c04a949 Convert to TCL IP 2020-07-01 19:43:26 -07:00
Alex Forencich
839ea23ac4 Fix arb mux header backpressure 2020-05-17 21:50:24 -07:00
Alex Forencich
d6ad22d435 Add DMA block diagram 2020-05-07 12:36:37 -07:00
Alex Forencich
b31c390d3e Assume tkeep[0] always high 2020-05-05 16:17:51 -07:00
Alex Forencich
4d4c7df5b6 Parametrize eth_axis_fcs 2020-05-05 16:13:02 -07:00
Alex Forencich
7d561c713f Update userspace utils 2020-05-01 21:55:50 -07:00
Alex Forencich
6d26adf916 Add MTU registers to driver 2020-05-01 21:54:44 -07:00
Alex Forencich
4e958096b2 Update driver model to set MTU registers 2020-05-01 19:19:56 -07:00
Alex Forencich
ae775a9386 Rewrite RX buffer management 2020-05-01 19:00:58 -07:00
Alex Forencich
8b535e54ac Add MTU registers 2020-05-01 18:55:01 -07:00
Alex Forencich
ca0cbf4d93 Update parameters 2020-05-01 17:22:21 -07:00
Alex Forencich
1f76606667 Move TDMA registers 2020-05-01 16:55:57 -07:00
Alex Forencich
ded213460d Rewrite TX buffer management 2020-05-01 14:29:52 -07:00
Alex Forencich
1c7b7937e5 Limit in-flight descriptor requests in TX engine 2020-04-30 23:37:41 -07:00
Alex Forencich
45ec6657b1 Limit in-flight descriptor requests in RX engine 2020-04-30 23:29:43 -07:00
Alex Forencich
d0c9a83752 Add google group link 2020-04-29 16:00:20 -07:00
Alex Forencich
31cec8d0c1 Fix cmac_pad frame truncation bug 2020-04-22 23:23:34 -07:00
Alex Forencich
6588d71d64 Increase PTP clock max adjust limit 2020-04-22 21:02:33 -07:00
Alex Forencich
9092e3c5cd Update mqnic-dump utility 2020-04-21 18:22:17 -07:00
Alex Forencich
e5dabc0cc5 Update readme 2020-04-21 18:06:20 -07:00
Alex Forencich
b62a47df8e Determine max desc block size and compute ring stride 2020-04-21 17:51:02 -07:00
Alex Forencich
a4108ecbf9 Implement TX scatter/gather in driver 2020-04-21 17:18:58 -07:00
Alex Forencich
a2ce454c22 Add log_desc_block_size to driver 2020-04-21 14:38:21 -07:00
Alex Forencich
9e64d19ea5 Use scatter descriptor blocks in driver model 2020-04-21 01:04:07 -07:00
Alex Forencich
2c6e9673f7 Add log_desc_block_size ring parameter in driver model 2020-04-21 00:58:12 -07:00
Alex Forencich
e14cfa0a58 Update port and interface modules 2020-04-20 21:25:21 -07:00
Alex Forencich
7087a595e9 Update RX and TX engines to support descriptor blocks 2020-04-20 21:24:25 -07:00
Alex Forencich
0fb60d718d Add log desc block size to desc_fetch module 2020-04-20 21:01:55 -07:00
Alex Forencich
d0cf549057 Add log desc block size field to queue manager 2020-04-20 20:45:10 -07:00
Alex Forencich
50af74aa88 Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH 2020-04-20 18:43:26 -07:00
Alex Forencich
4754d94736 Fix backpressure bug 2020-04-17 21:22:07 -07:00
Alex Forencich
4a50e1ec63 Add block diagram 2020-04-17 16:35:34 -07:00