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Author SHA1 Message Date
Alex Forencich
41f8667310 Add AXI write DMA module and testbenches 2018-12-27 14:15:51 -08:00
Alex Forencich
21ed77e4c0 Add AXI stream endpoint module 2018-12-27 13:49:48 -08:00
Alex Forencich
8b8cfd96fd merged changes in axis 2018-12-09 00:06:34 -08:00
Alex Forencich
59a979aeda Add parameters to testbench 2018-12-09 00:05:38 -08:00
Alex Forencich
8d9ed665d7 Use logical operator instead of bitwise 2018-12-09 00:04:56 -08:00
Alex Forencich
cadd1bcb50 Match width 2018-12-09 00:04:30 -08:00
Alex Forencich
aa6991a4a5 Bitwise operators instead of generate 2018-12-09 00:03:09 -08:00
Alex Forencich
3d90e80da8 Fix frame FIFO full logic bug 2018-12-09 00:01:38 -08:00
Alex Forencich
f9a5e6803b Add backpressure tests 2018-12-08 23:59:57 -08:00
Alex Forencich
50eb71221b Change cycle to segment, clean up parameters 2018-12-06 18:32:46 -08:00
Alex Forencich
fbec32e4f2 Use whole status FIFO memory 2018-12-06 17:36:12 -08:00
Alex Forencich
76fba3ac84 Add AXI central DMA module and testbenches 2018-12-06 17:27:44 -08:00
Alex Forencich
275cb09205 Minor reorganization 2018-12-06 17:19:30 -08:00
Alex Forencich
3587cf5285 Fix AXI memory model bug 2018-12-06 15:14:54 -08:00
Alex Forencich
e5e2aa8867 Use correct parameter 2018-12-06 01:21:42 -08:00
Alex Forencich
e7b6f43c8c Fix multi-driven net issue 2018-12-04 21:03:39 -08:00
Alex Forencich
7d0f3ef7a1 Fix address range overlap check to support arbitrary address widths 2018-12-04 17:00:26 -08:00
Alex Forencich
43234018cd Add AXI read DMA module and testbenches 2018-12-03 23:29:22 -08:00
Alex Forencich
61df54e62d Add M_REGIONS and M_SECURE parameters, add address range overlap check 2018-12-03 13:17:45 -08:00
Alex Forencich
7141a75ce8 Remove region inputs 2018-12-03 13:15:55 -08:00
Alex Forencich
b54d3eb866 Change cycle to segment, clean up parameters 2018-12-03 12:52:00 -08:00
Alex Forencich
f45a3ef5e0 Change cycle to segment 2018-12-03 12:40:06 -08:00
Alex Forencich
5db9cddf6e Reorganize and simplify burst length computation code 2018-11-29 15:20:01 -08:00
Alex Forencich
203771a5b8 merged changes in axis 2018-11-28 14:18:56 -08:00
Alex Forencich
a72d7bd260 Fix generate statement 2018-11-28 14:18:09 -08:00
Alex Forencich
8ab02e4220 Remove some debug code 2018-11-28 11:14:26 -08:00
Alex Forencich
89c8e87f95 Add status FIFO to manage write responses 2018-11-28 11:13:53 -08:00
Alex Forencich
c6f342ef01 Respect enable signal 2018-11-28 01:18:48 -08:00
Alex Forencich
0dbf0b1cff Add optional output pipeline register to AXI RAM module 2018-11-27 01:17:31 -08:00
Alex Forencich
89c52d4eec Fix bit width warning 2018-11-26 23:27:06 -08:00
Alex Forencich
061756f667 Add AXI stream mux module 2018-11-26 23:25:46 -08:00
Alex Forencich
28fa143ae5 Add Ultrascale PCIe DMA modules and testbenches 2018-11-26 23:23:54 -08:00
Alex Forencich
008a7167c7 Add AXI_MAX_BURST_SIZE parameter to PCIe AXI master 2018-11-26 18:03:54 -08:00
Alex Forencich
d81ee9487a Add some more comments 2018-11-26 15:56:13 -08:00
Alex Forencich
24f709573c Only store on valid transfer in 2018-11-26 13:18:38 -08:00
Alex Forencich
1dcc091201 Adjustments for 64 bit datapath 2018-11-26 13:17:41 -08:00
Alex Forencich
8c7eb13c0d Properly handle truncated packet 2018-11-26 13:12:50 -08:00
Alex Forencich
a6809a6b57 Use constants instead of magic numbers 2018-11-26 13:07:50 -08:00
Alex Forencich
fe8a4f9df3 Use constants for control characters 2018-11-11 00:18:32 -08:00
Alex Forencich
6a4b2699ea End frame reception on any control character 2018-11-11 00:11:27 -08:00
Alex Forencich
25e196e18b Insert idle characters 2018-11-10 18:56:50 -08:00
Alex Forencich
b195c6450b Add IFG parameter 2018-11-10 18:23:44 -08:00
Alex Forencich
a49b78b3c3 Add width asserts 2018-11-10 18:23:31 -08:00
Alex Forencich
b6c8cc7125 Append termination control character 2018-11-10 18:16:30 -08:00
Alex Forencich
0159376cda Simplify IFG count handling 2018-11-10 17:35:31 -08:00
Alex Forencich
d59a0553bd Change start character handling 2018-11-09 16:51:54 -08:00
Alex Forencich
261ad46a8a Add enable signals to xgmii model 2018-11-09 16:47:19 -08:00
Alex Forencich
c3d4aeda48 Use logical operators 2018-11-08 23:36:05 -08:00
Alex Forencich
6b85aed564 Any control characters in packet considered an error 2018-11-08 13:34:32 -08:00
Alex Forencich
ebe31e811c Use parameters for control characters 2018-11-08 13:15:47 -08:00