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437 Commits 1 Branch 0 Tags
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5 Commits

Author SHA1 Message Date
Alex Forencich
c62df81292 Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH 2022-02-15 00:39:46 -08:00
Alex Forencich
90959b8795 Add default_nettype none and resetall directives 2021-10-20 17:49:30 -07:00
Alex Forencich
8a6abc51ed Add statistics outputs to DMA interface 2021-09-05 15:29:56 -07:00
Alex Forencich
811b9daa63 Add missing connection 2021-08-11 19:18:50 -07:00
Alex Forencich
b95f030408 Add PCIe DMA interface modules and testbenches 2021-08-04 01:02:48 -07:00