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Author SHA1 Message Date
Alex Forencich
571394f99f Translate LPI control characters 2021-10-15 23:53:53 -07:00
Alex Forencich
5494f3b678 Rewrite resets 2021-10-15 23:33:35 -07:00
Alex Forencich
a540e50e1c Fix XGMII to BASE-R control character mapping 2021-10-15 16:14:02 -07:00
Alex Forencich
a539a76ec4 Add cocotb testbenches for 10G MAC+PHY modules 2021-10-15 01:37:10 -07:00
Alex Forencich
e7dddc0dfd Add cocotb testbenches for AXI stream BASE-R TX and RX modules 2021-10-15 01:08:14 -07:00
Alex Forencich
8b95b33bab Add cocotb testbench for 10G PHY 2021-10-15 01:07:26 -07:00
Alex Forencich
2d9f01f9fe Add cocotb testbenches for XGMII BASE-R encoder and decoder modules 2021-10-15 01:06:57 -07:00
Alex Forencich
c0e2eb2b07 Add BASE-R serdes models for cocotb 2021-10-15 00:36:56 -07:00
Alex Forencich
70cb88629b merged changes in axis 2021-10-13 18:17:45 -07:00
Alex Forencich
10e24cc5b1 Fix timing constraints 2021-10-13 18:07:45 -07:00
Alex Forencich
4c14289fb0 Fix instance name 2021-10-13 14:43:42 -07:00
Alex Forencich
e85deafca3 Update FIFO instance 2021-10-13 14:42:57 -07:00
Alex Forencich
1d187b9b87 merged changes in axis 2021-10-13 14:12:11 -07:00
Alex Forencich
4f1eabab17 Split async FIFO resets 2021-10-13 14:05:13 -07:00
Alex Forencich
e0da1819c4 More tests for pipeline FIFO 2021-09-28 01:18:17 -07:00
Alex Forencich
0b5fc5b0e0 Fix off by one error 2021-09-28 01:17:57 -07:00
Alex Forencich
e48901a588 Reorganize test lists 2021-09-28 01:17:28 -07:00
Alex Forencich
d549267e17 Test async FIFO with different clock periods 2021-09-28 00:29:54 -07:00
Alex Forencich
e8c28e00cd Update tox configuration 2021-09-13 13:02:17 -07:00
Alex Forencich
c44e447db5 Transfer PTP information in tuser 2021-09-01 15:56:00 -07:00
Alex Forencich
b6f792cc10 merged changes in axis 2021-09-01 15:54:12 -07:00
Alex Forencich
6c234260b2 Fix assignment type 2021-09-01 15:53:15 -07:00
Alex Forencich
3db970636c merged changes in axis 2021-08-27 15:28:53 -07:00
Alex Forencich
6bcd96fa83 Bypass pipeline FIFO when length is zero 2021-08-27 13:54:14 -07:00
Alex Forencich
e7de9b6ee6 Update PTP CDC instances 2021-08-26 01:07:56 -07:00
Alex Forencich
77938fa422 Update MAC modules for changes in FIFO modules 2021-08-26 00:55:12 -07:00
Alex Forencich
5273a8dda6 merged changes in axis 2021-08-26 00:14:22 -07:00
Alex Forencich
a613cc8a31 Fix alignment 2021-08-25 23:58:52 -07:00
Alex Forencich
6d70b0249e Update readme 2021-08-25 23:58:33 -07:00
Alex Forencich
6a030f5d5e Add axis_pipeline_fifo 2021-08-25 23:54:30 -07:00
Alex Forencich
92681fad8c Add DROP_OVERSIZE_FRAME parameter 2021-08-25 22:56:22 -07:00
Alex Forencich
0b2066abe3 Fix corner case with back-to-back single-cycle transfers 2021-08-25 19:19:30 -07:00
sungsoo.han
ceeea4b451 modify acknowledge assign 2021-08-17 16:42:26 +09:00
sungsoo.han
edaec3bd38 add LAST_ENABLE to axis_arb_mux 2021-08-17 16:00:23 +09:00
Alex Forencich
81673727a4 Fix broadcast address check 2021-08-08 13:25:39 -07:00
Alex Forencich
52d8867f73 Use BUFG instead of BUFIO2 for DDR input on Spartan 6 2021-07-31 12:45:38 -07:00
Alex Forencich
3edbe52bfa Use BUFG instead of BUFIO2 for DDR input on Spartan 6 2021-07-31 12:43:33 -07:00
Alex Forencich
29313d5e02 Add HTG-9200 10G example design 2021-07-08 11:58:04 -07:00
Alex Forencich
cf832f581c Set algorithm for pytest-split 2021-06-28 01:34:34 -07:00
Alex Forencich
97182ccf4e Update vivado.mk 2021-06-23 20:07:29 -07:00
Alex Forencich
763cc1669f Update test durations 2021-06-03 13:52:41 -07:00
Alex Forencich
5415c41c41 Remove string parameters 2021-06-02 17:50:26 -07:00
Alex Forencich
846183bc8b merged changes in axis 2021-06-02 17:06:26 -07:00
Alex Forencich
4fa3870dea Remove string parameters 2021-06-02 15:08:43 -07:00
Alex Forencich
0512664ae0 merged changes in axis 2021-06-01 13:03:13 -07:00
Alex Forencich
892ee84bff Delay command until write is acknowledged 2021-05-31 01:32:02 -07:00
Alex Forencich
3579310447 Clear active bit 2021-05-31 01:31:30 -07:00
Alex Forencich
e32f65f563 Update test durations 2021-05-30 12:39:49 -07:00
Alex Forencich
5d9c982cd4 Add switch testbenches 2021-05-30 12:33:29 -07:00
Alex Forencich
34d5a4fed5 Add wrapper generator for RAM switch 2021-05-30 12:32:26 -07:00