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Author SHA1 Message Date
Alex Forencich
364d835957 Split queue op tag table entry 2019-08-29 19:44:43 -07:00
Alex Forencich
ab07ab7ff7 Fix latch inference 2019-08-29 18:36:15 -07:00
Alex Forencich
d67c9ff70e Pull out scheduler op table size parameter 2019-08-23 07:44:33 -07:00
Alex Forencich
744ac22c75 Normalize queue op table sizes 2019-08-22 19:19:51 -07:00
Alex Forencich
6a354e7aa3 Normalize descriptor table sizes 2019-08-22 19:03:19 -07:00
Alex Forencich
5e0bf48b37 Update readme 2019-08-22 00:57:17 -07:00
Alex Forencich
3abb8d9534 Add TX checksum offload support to driver 2019-08-22 00:46:48 -07:00
Alex Forencich
a4132cfda7 Integrate TX checksum offload 2019-08-22 00:45:09 -07:00
Alex Forencich
3b6bca6b93 Add transmit checksum module and testbench 2019-08-21 22:57:41 -07:00
Alex Forencich
7b2a0d5032 Sync driver model 2019-08-20 01:36:22 -07:00
Alex Forencich
e548bd0238 Initialize RAMs 2019-08-20 01:06:29 -07:00
Alex Forencich
df4dbb75a1 Read interface feature bits in driver 2019-08-19 23:45:52 -07:00
Alex Forencich
d977cbdac2 Add feature bits 2019-08-19 23:43:52 -07:00
Alex Forencich
1fc15d234d Read interface and port features in userspace code 2019-08-19 23:29:09 -07:00
Alex Forencich
b77d21702a Read interface and port features in driver 2019-08-19 23:28:27 -07:00
Alex Forencich
5f066b9fcd Adjust ExaNIC board ID to match original PCIe ID 2019-08-19 22:04:10 -07:00
Alex Forencich
f5999faf60 Handle change in kernel API 2019-08-19 18:38:01 -07:00
Alex Forencich
35d73dde80 Add port activate and deactivate methods 2019-08-19 18:25:13 -07:00
Alex Forencich
7477cda192 Add port management code to userspace code 2019-08-19 16:00:29 -07:00
Alex Forencich
d8a2efc756 Add port management code to driver 2019-08-19 15:59:57 -07:00
Alex Forencich
0fd9bc7376 merged changes in pcie 2019-08-19 14:32:55 -07:00
Alex Forencich
68974e800b Fix completion handling bug 2019-08-19 14:31:08 -07:00
Alex Forencich
c9a17cdf90 Init scheduler queue state on reset 2019-08-13 13:51:50 -07:00
Alex Forencich
94c8dabad6 Rewrite scheduler 2019-08-13 00:45:01 -07:00
Alex Forencich
aeaabfeff5 Truncate high order address bits 2019-08-13 00:41:10 -07:00
Alex Forencich
80f06e1fcc Update testbenches 2019-08-13 00:39:28 -07:00
Alex Forencich
d99f40db08 Add port CSRs 2019-08-13 00:27:09 -07:00
Alex Forencich
451acd3af5 Parametrize queue RAM width 2019-08-11 15:15:55 -07:00
Alex Forencich
1e06d7cca7 Clean up pipeline parameters 2019-08-11 09:55:10 -07:00
Alex Forencich
46fe4bbd97 Remove extraneous code 2019-08-11 00:34:50 -07:00
Alex Forencich
f6244afdd2 Add symlink 2019-08-11 00:33:22 -07:00
Alex Forencich
2f27b5f0f1 Update timespec 2019-08-08 21:40:02 -07:00
Alex Forencich
59606f2cbf Pull I2C driver code into separate module 2019-08-08 21:31:29 -07:00
Alex Forencich
3e0c23f24f Update readme 2019-08-08 12:47:19 -07:00
Alex Forencich
afbec29b52 merged changes in pcie 2019-08-04 00:39:35 -07:00
Alex Forencich
564178a05a Automatically select port upstream of device when necessary 2019-08-04 00:38:38 -07:00
Alex Forencich
13835c18a1 merged changes in pcie 2019-08-03 23:33:15 -07:00
Alex Forencich
97500d10f6 Improved link speed control script 2019-08-03 23:32:02 -07:00
Alex Forencich
f1024f72cb merged changes in eth 2019-07-29 18:56:36 -07:00
Alex Forencich
cdfa01e2aa Add checksum verification methods 2019-07-29 18:54:37 -07:00
Alex Forencich
bfef06ca0e Separate UDP pseudo header checksum computation 2019-07-29 18:53:32 -07:00
Alex Forencich
2fbbfb05f9 Parametrize channel assignments 2019-07-28 16:02:54 -07:00
Alex Forencich
0709e4e09f Remove extraneous parameter 2019-07-28 16:01:05 -07:00
Alex Forencich
26f6774182 Parameter updates and documentation 2019-07-27 23:47:46 -07:00
Alex Forencich
772e01c95c Add VCU118 mqnic_tdma design 2019-07-25 20:24:32 -07:00
Alex Forencich
089a46c811 Add VCU118 mqnic design 2019-07-25 20:21:11 -07:00
Alex Forencich
5b8898f2bc Add VCU108 mqnic_tdma design 2019-07-25 17:44:13 -07:00
Alex Forencich
958aec8e8c Add VCU108 mqnic design 2019-07-25 17:05:56 -07:00
Alex Forencich
f518aec219 Include instance names in error messages 2019-07-25 16:38:54 -07:00
Alex Forencich
562e713837 Remove extraneous connections 2019-07-25 15:34:32 -07:00