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Author SHA1 Message Date
Alex Forencich
4410d74848 Update readme 2019-06-19 23:28:15 -07:00
Alex Forencich
1eb9c39ed3 Add VCU118 25G example design 2019-06-19 23:25:06 -07:00
Alex Forencich
1a28b0bf67 Add ADM-PCIE-9V3 25G example design 2019-06-19 23:22:56 -07:00
Alex Forencich
a031993b26 Update example designs 2019-06-19 23:16:57 -07:00
Alex Forencich
eb1f38a749 More critical path optimizations 2019-06-19 15:06:55 -07:00
Alex Forencich
134ce04777 Add configurable serdes pipeline register chain 2019-06-19 00:57:28 -07:00
Alex Forencich
3ba91ce091 Wait for block lock 2019-06-19 00:53:41 -07:00
Alex Forencich
303dec8165 Sum errors across data and header 2019-06-19 00:25:41 -07:00
Alex Forencich
1d3554c37e Rework pointer handling to improve timing 2019-06-16 23:53:26 -07:00
Alex Forencich
7ec836baf6 IP header checksum optimizations 2019-06-16 22:01:11 -07:00
Alex Forencich
b17966f73d store_last_word timing optimization 2019-06-16 20:01:08 -07:00
Alex Forencich
55bf44117b shift_axis_extra_cycle timing optimization 2019-06-16 19:57:52 -07:00
Alex Forencich
3b959b2765 CRC handling logic optimizations 2019-06-16 17:39:28 -07:00
Alex Forencich
320a45c4ab Remove unused state bit 2019-06-16 17:33:14 -07:00
Alex Forencich
8bb243cd35 MAC termination detect timing optimizations 2019-06-16 15:44:41 -07:00
Alex Forencich
4f97303e44 Remove unused code 2019-06-16 15:38:35 -07:00
Alex Forencich
938479c246 MAC RX timing optimizations 2019-06-16 00:36:50 -07:00
Alex Forencich
834d6a4b2d Improve timing for unaligned operations (shift_axis_extra_cycle) 2019-06-15 21:27:41 -07:00
Alex Forencich
27999924a0 Update VCU108 example designs 2019-06-15 17:35:49 -07:00
Alex Forencich
3684ccafb2 Make use of blocking statements consistent 2019-06-15 16:56:45 -07:00
Alex Forencich
b2cacc4e94 Update readme 2019-06-14 00:26:07 -07:00
Alex Forencich
d96a5a449a Update ARP cache testbench 2019-06-14 00:01:51 -07:00
Alex Forencich
ce13522085 Implement ARP cache clear 2019-06-14 00:01:13 -07:00
Alex Forencich
b41ab00381 Initialize ARP cache 2019-06-13 23:45:17 -07:00
Alex Forencich
296744b37e Make use of blocking statements consistent 2019-06-12 23:31:03 -07:00
Alex Forencich
209cb7d41d Fix completion handling 2019-06-12 21:29:19 -07:00
Alex Forencich
b0cda50aba Fix AXIL interconnect read bug 2019-06-12 17:57:39 -07:00
Alex Forencich
7ccd520d2c merged changes in axis 2019-06-10 17:45:02 -07:00
Alex Forencich
ced2df141c Add false path for async FIFO implementation in distributed RAM 2019-06-10 17:40:30 -07:00
Alex Forencich
75d9154d32 Reduce extraneous warnings from get_cells 2019-06-10 17:39:18 -07:00
Alex Forencich
6eff2f0030 Decouple transmit PTP tag enable and transmit PTP timestamp enable 2019-06-09 22:03:24 -07:00
Alex Forencich
20bb430ae9 merged changes in axis 2019-06-09 18:59:03 -07:00
Alex Forencich
ccc15324a6 Fix bad frame mask 2019-06-09 18:46:49 -07:00
Alex Forencich
2794c315e8 Fix synthesizer complaints 2019-06-08 17:36:09 -07:00
Alex Forencich
82fe5a6bdd Add PTP timestamp capture logic to MACs 2019-06-07 16:38:36 -07:00
Alex Forencich
659aa67481 Pack start packet strobes into the same signal 2019-06-06 17:13:14 -07:00
Alex Forencich
2efcfdb0a0 Add PTP clock simulation model 2019-06-03 19:08:16 -07:00
Alex Forencich
e181ea5abc Add PTP clock module and testbench 2019-06-03 19:00:28 -07:00
Alex Forencich
352f52e159 Add flash target to Arty example design 2019-05-27 01:02:55 -07:00
Alex Forencich
3da3725429 Disable bit slipping when RX PRBS check is enabled 2019-05-16 23:22:47 -07:00
Alex Forencich
5581a76c0b Use correct clocks 2019-05-14 18:57:01 -07:00
Alex Forencich
db8a2e1e96 Parametrize cycle count widths 2019-05-13 22:06:41 -07:00
Alex Forencich
74a75772ec Pipeline tag table write 2019-05-13 19:15:43 -07:00
Alex Forencich
249f9d9df4 Update example designs 2019-05-10 22:55:44 -07:00
Alex Forencich
79ec137243 Add PRBS31 generation and checking to 10G PHY 2019-05-10 20:28:45 -07:00
Alex Forencich
e34c72da1f Add missing parameter 2019-05-10 17:23:55 -07:00
Alex Forencich
b7d297850c Move 10G PHY interface logic into separate modules 2019-05-10 14:56:18 -07:00
Alex Forencich
6810c75723 Fix parameter 2019-05-09 23:20:36 -07:00
Alex Forencich
7b33dde069 Fix state encoding 2019-05-06 17:37:09 -07:00
Alex Forencich
2abb413854 Fix signal name 2019-05-02 20:30:37 -07:00