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Commit Graph

492 Commits

Author SHA1 Message Date
Alex Forencich
3cbb4a9506 merged changes in pcie 2021-09-08 10:05:40 -07:00
Alex Forencich
cef144e376 Expose DMA_LEN_WIDTH and DMA_TAG_WIDTH parameters 2021-09-08 00:18:11 -07:00
Alex Forencich
c00a53155d Fix alignment 2021-09-07 01:38:09 -07:00
Alex Forencich
bdd2312ecc More descriptive parameter and signal names for AXI lite control connections 2021-09-07 01:35:15 -07:00
Alex Forencich
8cf16c182b More descriptive parameter names (SYNC instead of INT) 2021-09-07 01:29:35 -07:00
Alex Forencich
15dec9458a Add statistics counter subsystem 2021-09-05 23:03:22 -07:00
Alex Forencich
9ccd43d470 Add statistics collection modules 2021-09-05 18:28:37 -07:00
Alex Forencich
65178395ed merged changes in pcie 2021-09-05 15:43:16 -07:00
Alex Forencich
5d760851ac Limit queue manager pipelines to a single AXI lite operation 2021-09-05 12:46:56 -07:00
Alex Forencich
ef00d5ccfd Add parameters for FIFO output pipeline register depth 2021-09-02 14:45:18 -07:00
Alex Forencich
f3eeb653d1 Fix test 2021-09-02 00:00:37 -07:00
Alex Forencich
600001b894 Update placement constraints 2021-09-01 16:10:39 -07:00
Alex Forencich
34ae6a9513 merged changes in eth 2021-09-01 16:10:05 -07:00
Alex Forencich
de869347cd Register interrupt signal 2021-09-01 13:14:02 -07:00
Alex Forencich
df9523011c Normalize instance names 2021-09-01 02:14:53 -07:00
Alex Forencich
09a10fc3ca Fix MAC clock period parameters 2021-09-01 02:06:25 -07:00
Alex Forencich
b630fdaeb0 Fix QSFP mapping comments 2021-09-01 02:01:14 -07:00
Alex Forencich
9295184e19 Fix signal width parametrization 2021-09-01 01:59:42 -07:00
Alex Forencich
fc835e0ab6 Use TX PTP CDC for both RX and TX due to synchronous clocking 2021-08-31 23:38:24 -07:00
Alex Forencich
82d0770daf Remove unused constraints file 2021-08-31 23:33:00 -07:00
Alex Forencich
c3d498101b Clarify widths 2021-08-31 23:32:42 -07:00
Alex Forencich
37a558e4f6 Add pipeline FIFOs 2021-08-31 22:30:45 -07:00
Alex Forencich
1fc991fc05 Convert fb2CG designs to use common core modules 2021-08-31 21:33:49 -07:00
Alex Forencich
915a915d6e Enable PCIe flow control in core tests 2021-08-31 20:38:08 -07:00
Alex Forencich
bd3fa6abfd Update vivado.mk 2021-08-31 20:03:33 -07:00
Alex Forencich
a5519cd607 Default to US+ configuration 2021-08-31 18:57:32 -07:00
Alex Forencich
bdbdc11841 Initial commit of core logic 2021-08-31 18:42:19 -07:00
Alex Forencich
9731ea5188 Add new PTP subsystem 2021-08-31 01:39:19 -07:00
Alex Forencich
cef2602efe Reorganize address space to place port registers in interface register space 2021-08-30 01:29:25 -07:00
Alex Forencich
d46cb16dbf Add scheduler block 2021-08-30 01:28:55 -07:00
Alex Forencich
d8615468e9 merged changes in eth 2021-08-30 01:28:13 -07:00
Alex Forencich
cee999a201 merged changes in axi 2021-08-30 01:28:08 -07:00
Alex Forencich
454d237ab2 Rename parameter 2021-08-30 01:27:53 -07:00
Alex Forencich
f71d28c6d8 Normalize RAM size and max frame size 2021-08-20 21:18:44 -07:00
Alex Forencich
4ceefa376a Normalize FIFO size to 32K 2021-08-20 21:17:41 -07:00
Alex Forencich
34150323df Remove obsolete packet table size parameters 2021-08-20 18:15:06 -07:00
Alex Forencich
43364943e1 merged changes in pcie 2021-08-20 16:10:32 -07:00
Alex Forencich
84e19ca305 Update file lists 2021-08-16 18:12:19 -07:00
Alex Forencich
fb241ae992 merged changes in pcie 2021-08-16 18:06:46 -07:00
Alex Forencich
38f766646b Connect flow control signals to pcie_us_if 2021-08-12 00:05:43 -07:00
Alex Forencich
6517d43ee7 Add missing connection 2021-08-11 23:52:44 -07:00
Alex Forencich
09c90e321b merged changes in pcie 2021-08-11 23:38:41 -07:00
Alex Forencich
a19474f9dd Use AXI lite crossbar 2021-08-11 01:31:34 -07:00
Alex Forencich
07292b7dda merged changes in axi 2021-08-11 01:28:07 -07:00
Alex Forencich
3e489fde27 Fix instance name 2021-08-04 12:37:13 -07:00
Alex Forencich
49aa27d1c5 Add placement constraints for AU50 2021-08-04 01:23:22 -07:00
Alex Forencich
0b65a1271a Use new PCIe DMA modules 2021-08-04 01:20:57 -07:00
Alex Forencich
038772b175 merged changes in pcie 2021-08-04 01:07:22 -07:00
Alex Forencich
e0e34a9f0d Update designs for PCIe module changes 2021-08-02 23:04:52 -07:00
Alex Forencich
6e178377c3 merged changes in pcie 2021-08-02 22:46:16 -07:00