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Author SHA1 Message Date
Alex Forencich
a7ebfdcebb Add arbitration test 2021-05-25 00:13:32 -07:00
Alex Forencich
b09e01ba48 Update S10MX SDC 2021-05-19 21:57:48 -07:00
Alex Forencich
9df253aa59 Update readme 2021-05-19 21:57:33 -07:00
Alex Forencich
cee82cb695 Add Stratix 10 DX 10G example design 2021-05-19 21:00:54 -07:00
Alex Forencich
13c1bbe79a Update S10MX QSF 2021-05-19 16:48:58 -07:00
Alex Forencich
0c493c4ba1 Update readme 2021-05-18 22:11:32 -07:00
Alex Forencich
28686fb115 Update readme 2021-05-18 22:05:44 -07:00
Alex Forencich
20c7967715 Update readme 2021-05-18 19:16:48 -07:00
Alex Forencich
bf6fddd1db Add Stratix 10 MX 10G example design 2021-05-18 19:16:30 -07:00
Alex Forencich
40265a3e1c Add timing constraints for Quartus Prime Pro 2021-05-18 18:30:33 -07:00
Alex Forencich
7751aba8da Reorganize timing constraints 2021-05-18 16:15:41 -07:00
Alex Forencich
f236e7dff1 merged changes in axis 2021-05-18 16:03:37 -07:00
Alex Forencich
b7f3faa628 Add timing constraints for Quartus Prime Pro 2021-05-18 16:02:36 -07:00
Alex Forencich
e9f7723312 Reorganize timing constraints 2021-05-16 23:28:00 -07:00
Alex Forencich
5e1329a992 Rework PHY bitslip timing 2021-05-05 00:35:43 -07:00
Alex Forencich
c021d01c26 Update example design readmes 2021-05-04 15:48:12 -07:00
Alex Forencich
244f136ca7 Remove travis-ci 2021-04-03 17:09:12 -07:00
Alex Forencich
b56bc11598 Update readme 2021-04-03 17:00:18 -07:00
Alex Forencich
397a253584 Add Github Actions regression testing 2021-04-03 16:57:14 -07:00
Alex Forencich
c884efc1f3 Add test durations for pytest-split 2021-04-03 16:56:54 -07:00
Alex Forencich
74c1014671 Add cocotb testbenches 2021-04-03 16:53:08 -07:00
Alex Forencich
17ba806687 Add tox and pytest configuration 2021-04-03 16:36:46 -07:00
Alex Forencich
9d99ec0096 Update wrapper generators 2021-04-03 16:34:42 -07:00
Alex Forencich
3df18fafdd Use nonblocking assignment 2021-04-03 16:33:45 -07:00
Alex Forencich
2796e681c9 Prevent latch inference 2021-03-30 22:23:40 -07:00
Alex Forencich
31c7349f90 Rewrite PTP clock CDC module for improved performance and timing closure at 25G 2021-03-30 15:57:46 -07:00
Alex Forencich
42950abf12 Refactor PTP period output, implement error output 2021-03-30 15:25:34 -07:00
Alex Forencich
00d69a341c Test with sample clock on and off 2021-03-27 14:44:36 -07:00
Alex Forencich
55359c1755 Report difference in ns 2021-03-27 14:44:21 -07:00
Alex Forencich
3cbe4b04da Improve timestamp difference measurement 2021-03-27 14:38:35 -07:00
Alex Forencich
1dd349399b PTP clock period is always positive 2021-03-17 21:13:36 -07:00
Alex Forencich
a3f6e36777 Use release version of cocotb for CI 2021-03-17 19:41:07 -07:00
Alex Forencich
6f81c27045 Add readme for Atlys example design 2021-03-16 13:52:01 -07:00
Alex Forencich
2446001807 Add cocotb testbenche for arp 2021-03-08 22:52:11 -08:00
Alex Forencich
f21f6296ac Add cocotb testbenches for arp_eth_rx and arp_eth_tx 2021-03-08 22:51:27 -08:00
Alex Forencich
20a56dc0d6 Refactor eth_axis_rx and eth_axis_tx testbenches 2021-03-08 22:47:40 -08:00
Alex Forencich
4af058fbdc Update testbenches 2021-03-06 20:04:19 -08:00
Alex Forencich
22b3bacf51 Update attribute name 2021-03-05 23:03:41 -08:00
Alex Forencich
c0c2dbce2a Update XDC files 2021-02-06 15:15:34 -08:00
Alex Forencich
eeb04acdd0 Update github actions 2021-01-16 13:39:56 -08:00
Alex Forencich
a91e2b7e17 Add KC705 SGMII example design 2020-12-30 17:15:34 -08:00
Alex Forencich
5a7fd98413 Add KC705 RGMII example design 2020-12-30 17:15:18 -08:00
Alex Forencich
8a021f5c9b Update KC705 XDC 2020-12-30 16:54:30 -08:00
Alex Forencich
22feb53e1d Update example design readmes 2020-12-30 16:48:37 -08:00
Alex Forencich
8e1ad2eba6 Add cocotb testbench for ptp_clock_cdc 2020-12-29 22:55:55 -08:00
Alex Forencich
7117de682a Add cocotb testbench for ptp_perout 2020-12-29 22:02:27 -08:00
Alex Forencich
0171afbb18 Add cocotb testbench for ptp_clock 2020-12-29 22:02:18 -08:00
Alex Forencich
e5bc5e1f49 Add cocotb testbench for arp_cache 2020-12-29 22:01:24 -08:00
Alex Forencich
25b890f8bb Remove extraneous code 2020-12-29 18:55:13 -08:00
Alex Forencich
77d22bfde0 Rework sim_build output directory, fix default makefile target 2020-12-29 14:47:12 -08:00