Alex Forencich
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782d86a7d1
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Remove readme link
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2020-12-28 20:43:26 -08:00 |
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Alex Forencich
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731fd859ac
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Add Github Actions regression tests
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2020-12-28 20:19:58 -08:00 |
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Alex Forencich
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4a98858bea
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Forward arguments to pytest
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2020-12-28 20:19:46 -08:00 |
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Alex Forencich
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f47c529122
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Add test durations
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2020-12-28 19:33:56 -08:00 |
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Alex Forencich
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cd12721502
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Add cococb testbenches for eth_axis_rx and eth_axis_tx
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2020-12-28 19:28:38 -08:00 |
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Alex Forencich
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29dc7498d3
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Add cocotb MAC testbenches
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2020-12-28 19:26:46 -08:00 |
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Alex Forencich
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0359d8d76a
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Use absolute path to test directory
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2020-12-28 19:25:59 -08:00 |
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Alex Forencich
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3a59569105
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Remove extraneous import
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2020-12-28 18:53:00 -08:00 |
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Alex Forencich
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db58c836f6
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Use absolute path to test directory
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2020-12-28 18:52:47 -08:00 |
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Alex Forencich
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a894af4815
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Add tox.ini
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2020-12-28 01:12:08 -08:00 |
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Alex Forencich
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079d6329cb
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Migrate example design testbenches to cocotb
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2020-12-28 01:11:03 -08:00 |
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Alex Forencich
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4d31316fef
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Remove travis-ci
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2020-12-25 02:09:50 -08:00 |
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Alex Forencich
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d1fc821c8b
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Fix simulation startup issue in rgmii_phy_if
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2020-12-25 02:03:57 -08:00 |
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Alex Forencich
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a78627343d
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Change default target parameter
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2020-12-25 01:48:24 -08:00 |
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Alex Forencich
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220e04d1a7
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Update example design
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2020-12-25 01:47:01 -08:00 |
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Alex Forencich
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2a2d8ac966
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Fix reg type in VCU108 and VCU118 example designs
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2020-12-20 14:22:52 -08:00 |
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Alex Forencich
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44bf507e24
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Update readme
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2020-12-19 14:59:02 -08:00 |
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Alex Forencich
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ba50df774d
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Add Github Actions regression tests
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2020-12-19 14:18:05 -08:00 |
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Alex Forencich
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8d7f4b52bf
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Add test durations
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2020-12-19 14:17:47 -08:00 |
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Alex Forencich
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0e0e9da047
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Add tox.ini
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2020-12-19 14:11:23 -08:00 |
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Alex Forencich
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a0a5ccc0a4
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Add cocotb testbenches
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2020-12-19 14:10:57 -08:00 |
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Alex Forencich
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7c19cb770d
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Properly name registers, CQ demux bug fix
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2020-12-19 14:09:56 -08:00 |
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Alex Forencich
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cabad17552
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Migrate example design testbenches to cocotb
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2020-12-18 22:10:32 -08:00 |
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Alex Forencich
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99e91c4d90
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Fix pointer handling issue in PCIe AXI DMA write module
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2020-12-18 18:37:53 -08:00 |
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Alex Forencich
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0c0fdc479b
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Update testbenches for async send/recv
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2020-12-18 17:40:36 -08:00 |
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Alex Forencich
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9ab1fb44b1
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Convert send/recv to blocking
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2020-12-18 16:50:50 -08:00 |
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Alex Forencich
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e3fb7d19b2
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Fix PCIe config
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2020-12-16 14:58:19 -08:00 |
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Alex Forencich
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ca7f0131ea
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Remove unnecessary __init__.py files
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2020-12-15 18:59:49 -08:00 |
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Alex Forencich
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af07083b1f
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Update readme
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2020-12-15 17:21:22 -08:00 |
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Alex Forencich
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26a9d484e8
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Add test durations
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2020-12-15 17:17:18 -08:00 |
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Alex Forencich
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c26bd5ef29
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Add Github Actions regresion testing
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2020-12-15 17:17:12 -08:00 |
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Alex Forencich
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f79b9d79ac
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Update readme
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2020-12-15 17:16:47 -08:00 |
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Alex Forencich
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eae1bcdc73
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Add tox.ini
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2020-12-15 16:54:49 -08:00 |
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Alex Forencich
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b5ee772761
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Migrate test infrastructure to cocotb
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2020-12-15 16:52:20 -08:00 |
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Alex Forencich
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3003b3228d
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Fix backpressure bug in TX checksum module
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2020-12-12 21:51:54 -08:00 |
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Alex Forencich
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be767f8ee7
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Update readme
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2020-12-04 16:18:28 -08:00 |
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Alex Forencich
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f8ff8a98d5
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Remove README symlink
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2020-12-04 16:15:32 -08:00 |
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Alex Forencich
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face7776d4
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Add Github Actions regresion testing
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2020-12-04 15:50:56 -08:00 |
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Alex Forencich
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bd4e574b36
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Add posargs to tox.ini
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2020-12-04 15:49:51 -08:00 |
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Alex Forencich
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5d2389fd81
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Add test durations for pytest-split
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2020-12-04 15:41:35 -08:00 |
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Alex Forencich
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de53699ed4
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Add top-level makefile
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2020-12-04 15:41:10 -08:00 |
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Alex Forencich
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72f5a2d1cb
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Add cocotb testbenches
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2020-12-04 15:32:14 -08:00 |
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Alex Forencich
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8fb827a18b
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Add tox and pytest configuration
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2020-12-04 15:30:48 -08:00 |
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Alex Forencich
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3d2364e19e
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Add wrapper generators
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2020-12-04 15:21:14 -08:00 |
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Alex Forencich
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d834e49587
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Move wire declarations
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2020-12-03 17:37:53 -08:00 |
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Alex Forencich
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1f9aa62639
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Add wrapper generator for axis_broadcast
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2020-12-03 17:31:11 -08:00 |
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Alex Forencich
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3240be1dd4
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Add pipeline registers, floorplanning constraints for AU250 100G design
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2020-12-03 15:08:57 -08:00 |
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Alex Forencich
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909ccae151
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Properly synchronize bad FCS status output
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2020-12-01 14:01:15 -08:00 |
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Alex Forencich
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91edbbf3dc
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Rename port and interface modules
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2020-11-26 15:05:59 -08:00 |
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Alex Forencich
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e4c4222fa9
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Use wlast instead of awlen to detect end of write burst
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2020-11-15 11:26:39 -08:00 |
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