22 Commits

Author	SHA1	Message	Date
Alex Forencich	db4d0a8f94	Timing optimizations	2020-02-27 20:00:37 -08:00
Alex Forencich	18bf537f4f	Fix register size	2020-02-27 15:47:18 -08:00
Alex Forencich	e14f6c6f0e	Remove unused signals	2019-12-13 15:33:12 -08:00
Alex Forencich	7567db1818	Add credit-based flow control to DMA cores	2019-12-06 23:24:36 -08:00
Alex Forencich	60a2813fbc	Fix indentation	2019-12-05 22:09:04 -08:00
Alex Forencich	8985c6dbf3	Add RQ sequence number inputs, operation table, TX_LIMIT parameter to ultrascale write DMA modules	2019-12-03 15:46:36 -08:00
Alex Forencich	546ef162dd	Rewrite reset	2019-11-26 16:44:46 -08:00
Alex Forencich	458a7fc598	Prioritize read request passthrough	2019-10-20 23:30:16 -07:00
Alex Forencich	553d7e05fe	Update AXI DMA modules to support 512 bit interface	2019-10-14 16:22:09 -07:00
Alex Forencich	a92722173a	Handle ultrascale plus interface widths	2019-10-04 16:29:11 -07:00
Alex Forencich	4c4119d44a	Use more correct parameters	2019-09-30 22:36:06 -07:00
Alex Forencich	e97e4ad423	Parametrize tuser signal widths	2019-09-26 23:30:03 -07:00
Alex Forencich	cddac11486	Bypass check when unnecessary	2019-09-26 14:38:21 -07:00
Alex Forencich	8f73b5605f	Fix check	2019-09-26 14:37:41 -07:00
Alex Forencich	e3ad96ef07	Add RQ channel passthrough to pcie_us_axi_dma_wr to eliminiate external mux	2019-09-17 16:32:47 -07:00
Alex Forencich	f518aec219	Include instance names in error messages	2019-07-25 16:38:54 -07:00
Alex Forencich	c75f29c648	Add parameter documentation	2019-07-24 18:01:13 -07:00
Alex Forencich	4afbd71f1f	Fanout optimization	2019-06-28 17:24:37 -07:00
Alex Forencich	db8a2e1e96	Parametrize cycle count widths	2019-05-13 22:06:41 -07:00
Alex Forencich	852d583282	Only store value when it is transferred	2019-01-02 01:59:29 -08:00
Alex Forencich	5db9cddf6e	Reorganize and simplify burst length computation code	2018-11-29 15:20:01 -08:00
Alex Forencich	28fa143ae5	Add Ultrascale PCIe DMA modules and testbenches	2018-11-26 23:23:54 -08:00