90 Commits

Author	SHA1	Message	Date
Alex Forencich	38c85a6bcd	Set subsystem ID based on board, remove unnecessary configuration settings	2021-11-02 15:32:55 -07:00
Alex Forencich	dbd15cb60e	Rework GT instances in VCU118 10G design	2021-10-21 22:16:05 -07:00
Alex Forencich	7ac4797336	Add default_nettype none and resetall directives	2021-10-20 21:53:39 -07:00
Alex Forencich	607257d7bb	Fix connections	2021-10-20 20:43:11 -07:00
Alex Forencich	982edfeda7	Update file lists	2021-10-20 19:37:37 -07:00
Alex Forencich	39fbc194fd	Update makefiles	2021-09-20 18:22:47 -07:00
Alex Forencich	f66f4d7cce	Update VCU118 designs	2021-09-13 00:09:23 -07:00
Alex Forencich	bd3fa6abfd	Update vivado.mk	2021-08-31 20:03:33 -07:00
Alex Forencich	d46cb16dbf	Add scheduler block	2021-08-30 01:28:55 -07:00
Alex Forencich	f71d28c6d8	Normalize RAM size and max frame size	2021-08-20 21:18:44 -07:00
Alex Forencich	34150323df	Remove obsolete packet table size parameters	2021-08-20 18:15:06 -07:00
Alex Forencich	84e19ca305	Update file lists	2021-08-16 18:12:19 -07:00
Alex Forencich	38f766646b	Connect flow control signals to pcie_us_if	2021-08-12 00:05:43 -07:00
Alex Forencich	6517d43ee7	Add missing connection	2021-08-11 23:52:44 -07:00
Alex Forencich	a19474f9dd	Use AXI lite crossbar	2021-08-11 01:31:34 -07:00
Alex Forencich	3e489fde27	Fix instance name	2021-08-04 12:37:13 -07:00
Alex Forencich	0b65a1271a	Use new PCIe DMA modules	2021-08-04 01:20:57 -07:00
Alex Forencich	e0e34a9f0d	Update designs for PCIe module changes	2021-08-02 23:04:52 -07:00
Alex Forencich	0a7f1ccbbe	Remove string parameters	2021-06-02 18:18:23 -07:00
Alex Forencich	15cb21dbd1	Reorganize timing constraints	2021-05-20 15:24:01 -07:00
Alex Forencich	7b2a0a1aed	Update testbenches	2021-04-28 20:54:44 -07:00
Alex Forencich	1bb5d8ab56	Add PTP support at 100G on VCU118	2021-04-01 18:02:58 -07:00
Alex Forencich	1aeeb0bbe2	Update designs for PTP CDC and Ethernet MAC module changes	2021-03-30 16:41:31 -07:00
Alex Forencich	32abea89fa	Update testbenches	2021-03-06 20:30:25 -08:00
Alex Forencich	d416e9f7fa	Roll back PCIe tag count to 64	2021-03-05 14:04:52 -08:00
Alex Forencich	a644d6dd3f	Update Vivado makefiles	2021-03-01 23:05:37 -08:00
Alex Forencich	d0b19efce5	Reconcile PCIe changes	2021-03-01 00:25:15 -08:00
Alex Forencich	a3c104f7dd	Connect write done signals	2021-02-24 15:07:26 -08:00
Alex Forencich	2779087de9	Constrain DMA muxes to same SLR	2021-02-23 02:17:10 -08:00
Alex Forencich	ceebb9f20e	Add more PCIe-related components to PCIe pblock	2021-02-23 00:55:05 -08:00
Alex Forencich	ea093b0126	More XDC cleanup	2021-02-06 15:15:05 -08:00
Alex Forencich	24d179dd4a	VCU118 XDC cleanup	2021-02-05 22:14:00 -08:00
Alex Forencich	b16fe8f7e7	More XDC clean up, add IO delay constraints for low speed IO	2021-02-05 16:08:23 -08:00
Alex Forencich	722bd929b8	Placement updates	2021-01-31 12:48:49 -08:00
Alex Forencich	151ed7e179	Add extra reset registers	2021-01-31 11:10:03 -08:00
Alex Forencich	972e41e433	Update placement constraints	2021-01-14 22:06:24 -08:00
Alex Forencich	7ede1d38e6	Update placement constraints for VCU118 100G design	2021-01-14 16:50:21 -08:00
Alex Forencich	6476ad3fd0	Separate file for placement constraints	2021-01-14 14:42:58 -08:00
Alex Forencich	b2ce3e4602	Add placement constraints for VCU118 10G design	2021-01-13 21:49:55 -08:00
Alex Forencich	42e19e1e96	Add pipeline registers, floorplanning constraints for VCU118 100G design	2021-01-13 20:55:20 -08:00
Alex Forencich	c0c2f933c0	Rework sim_build output directory, fix default makefile target	2020-12-29 17:28:53 -08:00
Alex Forencich	0c0fdc479b	Update testbenches for async send/recv	2020-12-18 17:40:36 -08:00
Alex Forencich	b5ee772761	Migrate test infrastructure to cocotb	2020-12-15 16:52:20 -08:00
Alex Forencich	91edbbf3dc	Rename port and interface modules	2020-11-26 15:05:59 -08:00
Alex Forencich	53f4275ea2	Add output registers for I2C interface to improve timing	2020-10-13 23:52:52 -07:00
Alex Forencich	ac4859d88e	Fix user_clk_frequency setting in testbenches	2020-10-12 23:07:43 -07:00
Alex Forencich	d6810db7f5	Add extra output register for flash interface to improve routability and timing	2020-10-08 19:22:28 -07:00
Alex Forencich	993a712f01	Update VCU118 XDC	2020-10-06 00:41:45 -07:00
Alex Forencich	5ecfe4bcca	Update flash programming configuration for VCU118	2020-10-05 17:12:45 -07:00
Alex Forencich	c2ded31ab7	Add QSPI flash access and IPROG for VCU118	2020-10-05 17:06:12 -07:00