FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity
938 Commits 1 Branch 0 Tags
Commit Graph

161 Commits

Author SHA1 Message Date
Alex Forencich
38e3244caa Rework GT instances in ExaNIC X10 design 2021-10-18 00:34:06 -07:00
Alex Forencich
fa77fe54f3 Rework GT instances in ExaNIC X25 design 2021-10-18 00:32:37 -07:00
Alex Forencich
4aa672f8f3 Update example designs 2021-10-17 20:20:26 -07:00
Alex Forencich
4c14289fb0 Fix instance name 2021-10-13 14:43:42 -07:00
Alex Forencich
e85deafca3 Update FIFO instance 2021-10-13 14:42:57 -07:00
Alex Forencich
29313d5e02 Add HTG-9200 10G example design 2021-07-08 11:58:04 -07:00
Alex Forencich
97182ccf4e Update vivado.mk 2021-06-23 20:07:29 -07:00
Alex Forencich
5415c41c41 Remove string parameters 2021-06-02 17:50:26 -07:00
Alex Forencich
b09e01ba48 Update S10MX SDC 2021-05-19 21:57:48 -07:00
Alex Forencich
cee82cb695 Add Stratix 10 DX 10G example design 2021-05-19 21:00:54 -07:00
Alex Forencich
13c1bbe79a Update S10MX QSF 2021-05-19 16:48:58 -07:00
Alex Forencich
bf6fddd1db Add Stratix 10 MX 10G example design 2021-05-18 19:16:30 -07:00
Alex Forencich
7751aba8da Reorganize timing constraints 2021-05-18 16:15:41 -07:00
Alex Forencich
c021d01c26 Update example design readmes 2021-05-04 15:48:12 -07:00
Alex Forencich
6f81c27045 Add readme for Atlys example design 2021-03-16 13:52:01 -07:00
Alex Forencich
c0c2dbce2a Update XDC files 2021-02-06 15:15:34 -08:00
Alex Forencich
a91e2b7e17 Add KC705 SGMII example design 2020-12-30 17:15:34 -08:00
Alex Forencich
5a7fd98413 Add KC705 RGMII example design 2020-12-30 17:15:18 -08:00
Alex Forencich
8a021f5c9b Update KC705 XDC 2020-12-30 16:54:30 -08:00
Alex Forencich
22feb53e1d Update example design readmes 2020-12-30 16:48:37 -08:00
Alex Forencich
77d22bfde0 Rework sim_build output directory, fix default makefile target 2020-12-29 14:47:12 -08:00
Alex Forencich
0359d8d76a Use absolute path to test directory 2020-12-28 19:25:59 -08:00
Alex Forencich
079d6329cb Migrate example design testbenches to cocotb 2020-12-28 01:11:03 -08:00
Alex Forencich
a78627343d Change default target parameter 2020-12-25 01:48:24 -08:00
Alex Forencich
220e04d1a7 Update example design 2020-12-25 01:47:01 -08:00
Alex Forencich
2a2d8ac966 Fix reg type in VCU108 and VCU118 example designs 2020-12-20 14:22:52 -08:00
Alex Forencich
306aa4db0b Update VCU118 XDC 2020-10-06 00:39:32 -07:00
Alex Forencich
ed7136a095 Update flash programming configuration for ExaNIC X10 and X25 2020-10-03 15:27:30 -07:00
Alex Forencich
9261f26f64 Update VCU108 XDC 2020-10-02 20:50:00 -07:00
Alex Forencich
9e4bd6e854 Fix flash programming commands for VCU108 2020-10-01 00:53:13 -07:00
Alex Forencich
816e071a57 Fix bitstream config for VCU1525 2020-09-30 23:50:31 -07:00
Alex Forencich
bf9f1a6211 Update flash programming commands 2020-09-29 18:29:27 -07:00
Alex Forencich
3f52ed675c Fix flash settings 2020-09-29 17:30:13 -07:00
Alex Forencich
2bc052e0d5 Update LED driver timing constraints 2020-09-28 17:24:11 -07:00
Alex Forencich
d0a45d8213 Add fb2CG flash programming commands 2020-09-27 01:45:56 -07:00
Alex Forencich
82cf0d5a6f Use correct init_clk frequency 2020-09-23 14:24:18 -07:00
Alex Forencich
6a4bcaab38 Add timing constraints for LED driver 2020-09-22 22:13:59 -07:00
Alex Forencich
a7972e32bb Add fb2CG 10G example design 2020-09-20 01:18:47 -07:00
Alex Forencich
4db7f50ad8 Update readme 2020-09-18 01:26:09 -07:00
Alex Forencich
c9a023c1e0 Add AU250 10G example design 2020-09-18 01:20:42 -07:00
Alex Forencich
6254158e1b Add AU200 10G example design 2020-09-18 01:20:20 -07:00
Alex Forencich
9a8ba2f0f2 Add ZCU102 example design 2020-09-18 00:15:21 -07:00
Alex Forencich
d97e95b6c7 Update XDC 2020-08-06 22:06:40 -07:00
Alex Forencich
df5368d153 Add ZCU106 example design 2020-08-06 18:26:07 -07:00
Alex Forencich
6aba3a741a Update makefiles 2020-08-06 17:19:11 -07:00
Alex Forencich
fd908dd2aa Clean up clock connections 2020-08-06 17:15:38 -07:00
Alex Forencich
f0e130aa48 Add AU50 10G example design 2020-07-17 00:06:32 -07:00
Alex Forencich
2570c75a0c Clean up AU280 design 2020-07-16 23:55:12 -07:00
Alex Forencich
f2f3c0f977 Add AU280 10G example design 2020-07-15 00:06:38 -07:00
Alex Forencich
b7c089dd22 XDC clean up 2020-07-13 23:58:30 -07:00