FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity
156 Commits 1 Branch 0 Tags
Commit Graph

156 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Alex Forencich
39200d84cb Update simulation models to support 512 bit interface 2019-10-14 15:45:41 -07:00
Alex Forencich
89ff925545 Timing optimizations 2019-10-14 14:00:55 -07:00
Alex Forencich
e96ee85356 Update example designs 2019-10-13 17:16:01 -07:00
Alex Forencich
2c43a6e189 Use mmap objects instead of bytearrays 2019-10-13 15:41:12 -07:00
Alex Forencich
75563c65f0 Add DMA interface mux modules 2019-10-12 23:08:21 -07:00
Alex Forencich
fdd7faef4f Add Xilinx Ultrascale PCIe DMA interface modules and testbenches 2019-10-12 23:03:42 -07:00
Alex Forencich
25de311347 Add DMA RAM module 2019-10-12 22:48:23 -07:00
Alex Forencich
e1035ed57d Add AXI stream sink DMA client module and testbench 2019-10-12 22:35:57 -07:00
Alex Forencich
baeeb8ea5c Add AXI stream source DMA client module and testbench 2019-10-12 22:34:15 -07:00
Alex Forencich
5e9254d519 Check is_eof_0 in RCSink 2019-10-12 18:58:27 -07:00
Alex Forencich
9b5a5db4d1 Add USPcieFrame intermediate format 2019-10-12 18:01:39 -07:00
Alex Forencich
603a6e18e2 Fix RC channel sideband byte enables 2019-10-11 14:16:44 -07:00
Alex Forencich
b7a505acfd Add segmented DMA RAM simulation model 2019-10-08 15:14:32 -07:00
Alex Forencich
a92722173a Handle ultrascale plus interface widths 2019-10-04 16:29:11 -07:00
Alex Forencich
e7630ef350 Expose parameter in wrapper 2019-10-02 23:21:49 -07:00
Alex Forencich
1b98af9364 Fix part-select range 2019-10-01 22:00:03 -07:00
Alex Forencich
295b6a507e Use constants instead of magic numbers 2019-10-01 17:30:09 -07:00
Alex Forencich
3817736aa1 Use constants instead of magic numbers 2019-10-01 17:24:18 -07:00
Alex Forencich
1b91200a4a Implement error code 2019-10-01 17:17:42 -07:00
Alex Forencich
b2d9a6a77f Add constants 2019-10-01 17:15:15 -07:00
Alex Forencich
4c4119d44a Use more correct parameters 2019-09-30 22:36:06 -07:00
Alex Forencich
7197e17445 Remove redundant code 2019-09-29 12:57:48 -07:00
Alex Forencich
836246ec4d Add missing asserts 2019-09-29 12:55:53 -07:00
Alex Forencich
e97e4ad423 Parametrize tuser signal widths 2019-09-26 23:30:03 -07:00
Alex Forencich
8678ecee65 Fix bug in AXI operation generation 2019-09-26 23:25:09 -07:00
Alex Forencich
e365ae44da Move AXI transfer size logic to improve timing 2019-09-26 14:39:31 -07:00
Alex Forencich
cddac11486 Bypass check when unnecessary 2019-09-26 14:38:21 -07:00
Alex Forencich
8f73b5605f Fix check 2019-09-26 14:37:41 -07:00
Alex Forencich
49f9524aeb Update testbenches 2019-09-17 21:46:54 -07:00
Alex Forencich
e3ad96ef07 Add RQ channel passthrough to pcie_us_axi_dma_wr to eliminiate external mux 2019-09-17 16:32:47 -07:00
Alex Forencich
68974e800b Fix completion handling bug 2019-08-19 14:31:08 -07:00
Alex Forencich
564178a05a Automatically select port upstream of device when necessary 2019-08-04 00:38:38 -07:00
Alex Forencich
97500d10f6 Improved link speed control script 2019-08-03 23:32:02 -07:00
Alex Forencich
f518aec219 Include instance names in error messages 2019-07-25 16:38:54 -07:00
Alex Forencich
c75f29c648 Add parameter documentation 2019-07-24 18:01:13 -07:00
Alex Forencich
7c500e6b6e Update axis_arb_mux 2019-07-24 17:52:53 -07:00
Alex Forencich
8f36c4a216 Update priority encoder 2019-07-24 14:23:04 -07:00
Alex Forencich
6e5a3934b2 Add get_free_tag methods 2019-07-15 20:38:09 -07:00
Alex Forencich
4bf1205514 Fix completion handling in function 2019-07-15 20:25:23 -07:00
Alex Forencich
a0bd74a198 Add Xilinx VCU118 example design 2019-07-15 17:24:50 -07:00
Alex Forencich
b0b51fdb34 Add Alpha Data ADM-PCIE-9V3 example design 2019-07-15 17:23:31 -07:00
Alex Forencich
f1348db2f7 Add Ultrascale Plus PCIe hard IP core model and testbench 2019-07-15 17:18:39 -07:00
Alex Forencich
1d79a4375b Add PCIe related scripts 2019-07-15 12:33:35 -07:00
Alex Forencich
b5e520e9da Add gitignore 2019-07-15 12:29:19 -07:00
Alex Forencich
d3b24e734f Don't use traceSignals 2019-07-14 21:45:10 -07:00
Alex Forencich
ece7186671 Fix typo 2019-07-14 21:41:21 -07:00
Alex Forencich
d99afcb2f1 Change tag count 2019-07-13 11:21:19 -07:00
Alex Forencich
9c176b0916 Add ExaNIC X10 example design 2019-07-13 11:06:29 -07:00
Alex Forencich
8ecf4a22ef Add pcie_us_cfg module 2019-07-13 10:24:25 -07:00
Alex Forencich
dcd8d7cd77 Update readme 2019-07-12 12:15:58 -07:00