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Code Issues Projects Releases Wiki Activity
2,912 Commits 1 Branch 0 Tags
Commit Graph

270 Commits

Author SHA1 Message Date
Alex Forencich
46fe4bbd97 Remove extraneous code 2019-08-11 00:34:50 -07:00
Alex Forencich
f6244afdd2 Add symlink 2019-08-11 00:33:22 -07:00
Alex Forencich
0709e4e09f Remove extraneous parameter 2019-07-28 16:01:05 -07:00
Alex Forencich
26f6774182 Parameter updates and documentation 2019-07-27 23:47:46 -07:00
Alex Forencich
ea7ccd182e Move MAC out of port module 2019-07-19 23:29:03 -07:00
Alex Forencich
eb92578699 Update FIFO instances 2019-07-19 16:17:36 -07:00
Alex Forencich
4b37a4484d Add TDMA round-robin scheduler 2019-07-19 15:40:53 -07:00
Alex Forencich
4c3f2412df Add TDMA BERT modules and testbenches 2019-07-19 15:28:57 -07:00
Alex Forencich
fcd8b1b8e9 Add driver simulation model 2019-07-17 16:46:12 -07:00
Alex Forencich
ce011453d6 Add interface module 2019-07-17 16:43:12 -07:00
Alex Forencich
351404813a Add port module 2019-07-17 16:42:39 -07:00
Alex Forencich
65f0ff28b5 Add Ethernet interface module 2019-07-17 16:41:21 -07:00
Alex Forencich
12f215fe26 Add round robin transmit scheduler 2019-07-17 16:40:35 -07:00
Alex Forencich
bda4e87371 Add event management modules 2019-07-17 16:39:59 -07:00
Alex Forencich
f94e83e520 Add transmit and receive engines 2019-07-17 16:38:57 -07:00
Alex Forencich
6100e3ad78 Add RX checksum module and testbench 2019-07-16 00:42:49 -07:00
Alex Forencich
a653f2d839 Add TDMA scheduler module and testbench 2019-07-16 00:19:22 -07:00
Alex Forencich
fc9a6c1c50 Add completion queue manager module and testbench 2019-07-16 00:16:07 -07:00
Alex Forencich
46f653f097 Add queue manager module and testbench 2019-07-16 00:15:50 -07:00
Alex Forencich
3d4ba0fa3f Add testbench symlinks 2019-07-16 00:15:25 -07:00