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1,983 Commits 1 Branch 0 Tags
Commit Graph

421 Commits

Author SHA1 Message Date
Alex Forencich
275c0e98e9 Add PTP support at 100G on Alveo U250 2021-04-01 16:53:00 -07:00
Alex Forencich
77bb4b9dd8 Add PTP support at 100G on Alveo U200 2021-04-01 16:52:00 -07:00
Alex Forencich
2975e075d4 Add PTP support at 100G on Alveo U280 2021-04-01 16:31:23 -07:00
Alex Forencich
31c902685a Add PTP support at 100G on fb2CG@KU15P 2021-04-01 16:29:52 -07:00
Alex Forencich
8b70695fa0 merged changes in eth 2021-03-30 22:25:28 -07:00
Alex Forencich
5d6723cc69 merged changes in pcie 2021-03-30 21:54:12 -07:00
Alex Forencich
c7896bef92 Use correct assignment type 2021-03-30 21:50:25 -07:00
Alex Forencich
2afbd1f15b Enable PTP in 25G designs 2021-03-30 18:53:52 -07:00
Alex Forencich
1aeeb0bbe2 Update designs for PTP CDC and Ethernet MAC module changes 2021-03-30 16:41:31 -07:00
Alex Forencich
1c9430823b merged changes in pcie 2021-03-30 16:20:33 -07:00
Alex Forencich
7993bc0125 merged changes in axi 2021-03-30 16:20:28 -07:00
Alex Forencich
f673470cf2 merged changes in eth 2021-03-30 16:20:04 -07:00
Alex Forencich
32abea89fa Update testbenches 2021-03-06 20:30:25 -08:00
Alex Forencich
c620cd23e7 merged changes in pcie 2021-03-06 20:29:02 -08:00
Alex Forencich
48e1c39e3f merged changes in eth 2021-03-06 20:27:23 -08:00
Alex Forencich
cd8566a6bc merged changes in axi 2021-03-06 20:27:13 -08:00
Alex Forencich
d416e9f7fa Roll back PCIe tag count to 64 2021-03-05 14:04:52 -08:00
Alex Forencich
705133bf7a Add SPI interface to Gecko BMC on fb2CG@KU15P 2021-03-04 22:34:52 -08:00
Alex Forencich
a644d6dd3f Update Vivado makefiles 2021-03-01 23:05:37 -08:00
Alex Forencich
d0b19efce5 Reconcile PCIe changes 2021-03-01 00:25:15 -08:00
Alex Forencich
421dbd5d0f merged changes in pcie 2021-03-01 00:03:44 -08:00
Alex Forencich
a3c104f7dd Connect write done signals 2021-02-24 15:07:26 -08:00
Alex Forencich
65fdc332b3 merged changes in pcie 2021-02-24 15:03:37 -08:00
Alex Forencich
365d39990d merged changes in eth 2021-02-24 15:03:24 -08:00
Alex Forencich
6bc757dbc0 merged changes in axi 2021-02-24 15:03:08 -08:00
Alex Forencich
4b3d153cbd Add placement constraints for fb2CG@KU15P 2021-02-23 02:33:37 -08:00
Alex Forencich
2779087de9 Constrain DMA muxes to same SLR 2021-02-23 02:17:10 -08:00
Alex Forencich
ceebb9f20e Add more PCIe-related components to PCIe pblock 2021-02-23 00:55:05 -08:00
Alex Forencich
6ab66ed347 Fix signal name in xdc 2021-02-14 15:08:13 -08:00
Alex Forencich
ea093b0126 More XDC cleanup 2021-02-06 15:15:05 -08:00
Alex Forencich
46149bef3f Update ZCU106 XDC 2021-02-05 22:22:25 -08:00
Alex Forencich
24d179dd4a VCU118 XDC cleanup 2021-02-05 22:14:00 -08:00
Alex Forencich
0c1acadbfa Enable termination on LVDS clock input 2021-02-05 22:12:59 -08:00
Alex Forencich
1d7dc703b5 Add cfgmclk timing constraints, rework reset connections 2021-02-05 18:00:56 -08:00
Alex Forencich
b16fe8f7e7 More XDC clean up, add IO delay constraints for low speed IO 2021-02-05 16:08:23 -08:00
Alex Forencich
816689035c Add placement constraints for ADM-PCIE-9V3 2021-02-05 16:06:56 -08:00
Alex Forencich
9e27d45959 Add IPROG for ADM-PCIE-9V3 2021-02-05 16:06:34 -08:00
Alex Forencich
89d7042aeb Add CMS IP to all Alveo designs 2021-01-31 14:17:49 -08:00
Alex Forencich
722bd929b8 Placement updates 2021-01-31 12:48:49 -08:00
Alex Forencich
151ed7e179 Add extra reset registers 2021-01-31 11:10:03 -08:00
Alex Forencich
1248ca1a2e Add power budget to Alveo XDC files 2021-01-29 15:44:15 -08:00
Alex Forencich
2a24722d7f Add placement constraints for ADM-PCIE-9V3 2021-01-15 22:36:46 -08:00
Alex Forencich
972e41e433 Update placement constraints 2021-01-14 22:06:24 -08:00
Alex Forencich
93400bf05d Update placement constraints for AU250 100G design 2021-01-14 17:19:40 -08:00
Alex Forencich
7ede1d38e6 Update placement constraints for VCU118 100G design 2021-01-14 16:50:21 -08:00
Alex Forencich
6476ad3fd0 Separate file for placement constraints 2021-01-14 14:42:58 -08:00
Alex Forencich
9accebffb9 Add pipeline registers, floorplanning constraints for AU200 100G design 2021-01-13 22:56:10 -08:00
Alex Forencich
9d97bf5a70 Add placement constraints for AU200 10G design 2021-01-13 22:14:18 -08:00
Alex Forencich
de76c82186 Add placement constraints for VCU118 10G mqnic_tdma design 2021-01-13 21:50:32 -08:00
Alex Forencich
b2ce3e4602 Add placement constraints for VCU118 10G design 2021-01-13 21:49:55 -08:00