18 Commits

Author	SHA1	Message	Date
Alex Forencich	b9e0af3634	Revert change to early ready conditions for improved throughput ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-09-18 12:07:11 -07:00
Alex Forencich	6d4458e5cc	Rewrite early ready condition ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-05-15 17:36:00 -07:00
Alex Forencich	268d0c66b8	Rewrite resets ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-05-13 12:57:41 -07:00
Alex Forencich	073d50d9dc	Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8	2022-03-30 16:02:17 -07:00
Alex Forencich	2972a1fa81	Add default_nettype none and resetall directives	2021-10-20 15:33:38 -07:00
Alex Forencich	ce00df8de1	Include instance names in error messages	2019-07-25 16:30:10 -07:00
Alex Forencich	c5f44c70d1	Add parameter documentation	2019-07-24 13:54:21 -07:00
Alex Forencich	e0a1a73ce0	Mask tdata with tkeep	2019-07-18 11:01:00 -07:00
Alex Forencich	d1ed1528b5	Update FIFO instance, rename ports	2018-10-25 10:15:16 -07:00
Alex Forencich	5df7efe516	Happy new year	2018-02-26 12:25:20 -08:00
Alex Forencich	772e433ee9	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame length adjuster	2017-11-20 21:30:26 -08:00
Alex Forencich	aebe0549dd	Happy new year	2017-05-18 13:35:11 -07:00
Alex Forencich	52fc34d82e	Assume first tkeep bit is always set	2016-07-20 12:36:59 -07:00
Alex Forencich	be4034071b	Happy new year	2016-01-05 00:24:20 -08:00
Alex Forencich	0d22a35bd8	Update output registers, remove extraneous resets, fix constant widths	2015-11-08 23:05:38 -08:00
Alex Forencich	dcad442e7c	Improve timing performance of frame length adjust module	2015-10-19 00:30:50 -07:00
Alex Forencich	ca11618e6d	Convert to synchronous resets	2015-10-08 11:26:32 -07:00
Alex Forencich	c15761068a	Add AXI stream frame length adjust modules	2015-06-05 17:04:10 -07:00