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Commit Graph

21 Commits

Author SHA1 Message Date
Alex Forencich
8e60adf567 Update axis_switch instances 2021-11-29 14:43:01 -08:00
Alex Forencich
74f32c6a59 Add missing PHY instance ports 2021-11-02 20:28:26 -07:00
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
05770c5a1b Rework GT instances in VCU118 designs 2021-10-19 22:13:02 -07:00
Alex Forencich
5415c41c41 Remove string parameters 2021-06-02 17:50:26 -07:00
Alex Forencich
2a2d8ac966 Fix reg type in VCU108 and VCU118 example designs 2020-12-20 14:22:52 -08:00
Alex Forencich
fd908dd2aa Clean up clock connections 2020-08-06 17:15:38 -07:00
Alex Forencich
a27c04a949 Convert to TCL IP 2020-07-01 19:43:26 -07:00
Alex Forencich
27ed447005 Use common sync_reset module files 2020-03-27 18:27:45 -07:00
Alex Forencich
a55c354924 Parametrize Ethernet frame parsing 2020-02-21 21:37:57 -08:00
Alex Forencich
c5e886769a Fix typo 2019-07-19 10:29:55 -07:00
Alex Forencich
16e5ec2106 Update example designs 2019-07-18 17:13:47 -07:00
Alex Forencich
5428d81fd6 Update AXI stream switch instances 2019-03-28 23:56:06 -07:00
Alex Forencich
e120a85607 Use correct clock 2019-03-28 17:56:55 -07:00
Alex Forencich
52058cb5de Swap out PHY in VCU118 example design 2019-02-05 18:28:42 -08:00
Alex Forencich
e882ed143f Update example designs 2018-11-08 09:20:33 -08:00
Alex Forencich
0a6bee6d69 Update example designs 2018-11-08 09:17:29 -08:00
Alex Forencich
7d6889add6 Update example designs 2018-10-30 21:32:32 -07:00
Alex Forencich
8982b4f4e1 Fix modsell pin 2018-06-29 13:00:41 -07:00
Alex Forencich
cd51821bf7 Add parameters 2018-06-22 18:56:05 -07:00
Alex Forencich
8e1f14e9a7 Add VCU118 10G example design 2018-06-13 19:30:07 -07:00