Alex Forencich
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3bbf8524d6
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Compute DEST_WIDTH
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2018-10-24 22:21:31 -07:00 |
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Alex Forencich
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9d813226d0
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Convert generated demux to verilog parametrized demux
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2018-10-24 22:16:05 -07:00 |
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Alex Forencich
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145ea2c40c
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Connect arbiter parameters to top level
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2018-10-24 21:09:00 -07:00 |
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Alex Forencich
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2bf15706cd
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Convert generated mux to verilog parametrized mux
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2018-10-24 18:23:14 -07:00 |
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Alex Forencich
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029d1fa06f
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Fix loop count variable scoping issue
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2018-10-24 17:58:39 -07:00 |
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Alex Forencich
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fc6c07e5f9
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Convert generated frame joiner to verilog parametrized frame joiner
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2018-10-24 17:07:22 -07:00 |
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Alex Forencich
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fd7f65d5ad
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Convert generated switch to verilog parametrized switch
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2018-10-24 16:12:56 -07:00 |
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Alex Forencich
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631147069f
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Rename ports and add reg_type parameter to axis_register
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2018-10-24 14:35:08 -07:00 |
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Alex Forencich
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940c1210c1
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Convert arbitrated mux to verilog parametrized arbitrated mux
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2018-10-24 13:49:17 -07:00 |
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Alex Forencich
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fe77db822d
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Convert generated crosspoint to verilog parametrized crosspoint
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2018-10-24 13:44:39 -07:00 |
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Alex Forencich
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553547f661
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Fix test naming
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2018-09-09 13:52:13 -07:00 |
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Alex Forencich
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becfbf4425
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When pausing the AXI stream model, do not drop tvalid if it is asserted and waiting for tready to be asserted
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2018-08-15 00:11:39 -07:00 |
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Alex Forencich
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8e5ec36ced
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Optimize axis_arb_mux and improve latency
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2018-08-09 18:40:50 -07:00 |
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Alex Forencich
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7a879aec1c
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Remove extra registers
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2018-08-09 18:38:41 -07:00 |
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Alex Forencich
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202fbcbb6f
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Fix typo
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2018-08-09 11:23:27 -07:00 |
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Alex Forencich
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ffc63e4b0d
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Update readme
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2018-07-02 16:25:29 -07:00 |
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Alex Forencich
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3063bba54b
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Update testbenches to use wait
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2018-07-02 16:19:35 -07:00 |
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Alex Forencich
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9390c3639b
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More endpoint updates
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2018-07-02 14:13:47 -07:00 |
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Alex Forencich
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268d011b89
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Add wait method to sink
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2018-06-30 00:21:26 -07:00 |
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Alex Forencich
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2ebffeb223
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Be more pythonic
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2018-06-30 00:21:02 -07:00 |
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Alex Forencich
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c5837daa2f
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Update testbenches to use instances()
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2018-06-13 22:26:10 -07:00 |
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Alex Forencich
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7c6da337b0
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Happy new year
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2018-02-27 01:39:25 -08:00 |
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Alex Forencich
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5df7efe516
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Happy new year
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2018-02-26 12:25:20 -08:00 |
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Alex Forencich
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c33985d7ba
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Remove extraneous parameter
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2017-11-21 08:54:21 -08:00 |
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Alex Forencich
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93688dc88e
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Update readme
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2017-11-21 00:21:15 -08:00 |
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Alex Forencich
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4ec4c901e8
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Whitespace fixes
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2017-11-21 00:18:09 -08:00 |
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Alex Forencich
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b00eaf4d3c
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Add tkeep signal and update testbench for stat counter
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2017-11-21 00:17:42 -08:00 |
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Alex Forencich
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ad0e3e1eb5
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Whitespace fixes and testbench update for frame joiner
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2017-11-21 00:16:15 -08:00 |
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Alex Forencich
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a1a6d523e3
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Update FIFO instances and testbenches for COBS encoder and decoder
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2017-11-21 00:14:26 -08:00 |
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Alex Forencich
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0edafd58ac
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream tap
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2017-11-20 23:45:34 -08:00 |
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Alex Forencich
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4ef4ef2622
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL register
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2017-11-20 21:34:25 -08:00 |
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Alex Forencich
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b0d7820f5b
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL FIFO
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2017-11-20 21:32:46 -08:00 |
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Alex Forencich
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d16f19f67e
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream rate limiter
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2017-11-20 21:31:41 -08:00 |
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Alex Forencich
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772e433ee9
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame length adjuster
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2017-11-20 21:30:26 -08:00 |
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Alex Forencich
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de590517a9
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream switch
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2017-11-20 20:17:20 -08:00 |
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Alex Forencich
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91a7169f46
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream crosspoint
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2017-11-20 20:16:21 -08:00 |
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Alex Forencich
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496c63bd1c
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream arbitrated mux
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2017-11-20 20:15:08 -08:00 |
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Alex Forencich
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57e700f802
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream demux
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2017-11-20 20:14:20 -08:00 |
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Alex Forencich
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9e4aa38750
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream mux
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2017-11-20 20:13:53 -08:00 |
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Alex Forencich
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d50c767482
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream adapter
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2017-11-20 20:12:43 -08:00 |
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Alex Forencich
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fdb881719c
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream async frame FIFO
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2017-11-20 20:12:02 -08:00 |
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Alex Forencich
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1c7362c717
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame FIFO
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2017-11-20 20:11:44 -08:00 |
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Alex Forencich
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7d237f55c1
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream async FIFO
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2017-11-20 20:11:08 -08:00 |
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Alex Forencich
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190d75df9d
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream FIFO
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2017-11-20 20:10:41 -08:00 |
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Alex Forencich
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a5524287ca
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream register
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2017-11-20 20:09:48 -08:00 |
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Alex Forencich
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a0b21db746
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Improve checks in axis_ep
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2017-11-20 15:43:54 -08:00 |
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Alex Forencich
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c9cc9006a3
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Add last_cycle_user parameter to axis_ep
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2017-11-20 15:43:32 -08:00 |
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Alex Forencich
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cb2221b39b
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Use correct path
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2017-11-12 18:36:15 -08:00 |
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Alex Forencich
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a51109c7c4
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Use latest python
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2017-11-12 18:30:08 -08:00 |
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Alex Forencich
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a35d1a8e7c
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Fix CI
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2017-11-12 18:22:41 -08:00 |
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