Alex Forencich
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3f334dbbbb
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Use MSI-X in example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-12 23:32:51 -07:00 |
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Alex Forencich
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e2588cd995
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Clean up TCL scripts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-12 16:23:54 -07:00 |
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Alex Forencich
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a17c33e3c6
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Update example designs to enable TLP straddling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-04 01:31:15 -07:00 |
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Alex Forencich
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19b1af0388
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Update Xilinx UltraScale shims to support TLP straddling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-04 00:46:07 -07:00 |
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Alex Forencich
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ee59fc10e0
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Update testbenches for new version of cocotbext-pcie
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-06-05 13:26:27 -07:00 |
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Alex Forencich
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ba5188dd93
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Update testbenches for new version of cocotbext-pcie
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-06-02 23:33:52 -07:00 |
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Alex Forencich
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0b815522b0
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Sync example design testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-20 00:43:55 -07:00 |
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Alex Forencich
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e4b1df0ddb
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Fix immediate enable register implementation in example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-20 00:43:21 -07:00 |
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Alex Forencich
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32b4f2cb1f
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Improve block operation tests
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2022-04-04 15:21:25 -07:00 |
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Alex Forencich
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e7a83364d0
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Update testbenches
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2022-04-04 15:05:21 -07:00 |
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Alex Forencich
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6e5f9f33f2
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Add example design for Alveo U200
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2021-11-18 16:25:59 -08:00 |
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