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Author SHA1 Message Date
Alex Forencich
1b147ff7c8 Add shared utility code 2019-07-21 21:53:37 -07:00
Alex Forencich
762037e8a8 Updates to be able to share header with userspace code 2019-07-21 21:51:14 -07:00
Alex Forencich
a6c4b8b1b7 Change board IDs 2019-07-21 15:27:01 -07:00
Alex Forencich
851eb2f25e Update readme 2019-07-20 00:56:21 -07:00
Alex Forencich
ea7ccd182e Move MAC out of port module 2019-07-19 23:29:03 -07:00
Alex Forencich
1917ed3912 merged changes in eth 2019-07-19 18:17:57 -07:00
Alex Forencich
ab77ac3858 Fix width 2019-07-19 18:16:07 -07:00
Alex Forencich
451db171d1 Don't leave output floating 2019-07-19 18:13:30 -07:00
Alex Forencich
9de2101cdc Update ExaNIC X10 testbenches 2019-07-19 18:01:24 -07:00
Alex Forencich
eb92578699 Update FIFO instances 2019-07-19 16:17:36 -07:00
Alex Forencich
00ebe73bdc merged changes in eth 2019-07-19 15:52:41 -07:00
Alex Forencich
36b3dccb6a Add mqnic-fw utility 2019-07-19 15:48:33 -07:00
Alex Forencich
578abab3de Add mqnic-config utility 2019-07-19 15:46:56 -07:00
Alex Forencich
5b15f03f69 Add ADM-PCIE-9V3 mqnic_tdma design 2019-07-19 15:43:40 -07:00
Alex Forencich
a9179dc550 Add ExaNIC X10 mqnic_tdma design 2019-07-19 15:42:18 -07:00
Alex Forencich
4b37a4484d Add TDMA round-robin scheduler 2019-07-19 15:40:53 -07:00
Alex Forencich
750112ff06 Add ADM-PCIE-9V3 mqnic design 2019-07-19 15:39:40 -07:00
Alex Forencich
4c3f2412df Add TDMA BERT modules and testbenches 2019-07-19 15:28:57 -07:00
Alex Forencich
c5e886769a Fix typo 2019-07-19 10:29:55 -07:00
Alex Forencich
16d1662d98 Add PTP timestamping infrastructure to 10G MACs 2019-07-18 23:13:46 -07:00
Alex Forencich
4e49dbcf3d Pass parameters to model 2019-07-18 22:51:54 -07:00
Alex Forencich
8cb0a5e06e Add parameters for PTP clock model 2019-07-18 22:49:29 -07:00
Alex Forencich
16755720d3 Add PTP tag inserter module 2019-07-18 22:39:50 -07:00
Alex Forencich
b26f923c2f Reset synchronizers 2019-07-18 18:35:30 -07:00
Alex Forencich
adb9c4d147 Fix initial values 2019-07-18 18:35:11 -07:00
Alex Forencich
16e5ec2106 Update example designs 2019-07-18 17:13:47 -07:00
Alex Forencich
3bd7be44fa Update FIFO instances and update MACs to use combined FIFO adapter module 2019-07-18 16:25:49 -07:00
Alex Forencich
3a79b8fb17 merged changes in axis 2019-07-18 11:50:56 -07:00
Alex Forencich
8b2f37d5cc Update readme 2019-07-18 11:28:19 -07:00
Alex Forencich
69de6fd2a4 Convert FIFOs to use DEPTH parameter instead of ADDR_WIDTH 2019-07-18 11:27:25 -07:00
Alex Forencich
e0a1a73ce0 Mask tdata with tkeep 2019-07-18 11:01:00 -07:00
Alex Forencich
4da1a83052 Constant FIFO depth 2019-07-17 23:36:10 -07:00
Alex Forencich
905651d5f8 Add PTP perout utility 2019-07-17 18:48:50 -07:00
Alex Forencich
6c5b6c99a1 Initial commit of mqnic kernel module 2019-07-17 18:13:51 -07:00
Alex Forencich
1df012a8d4 Add ExaNIC X10 design 2019-07-17 16:57:04 -07:00
Alex Forencich
fcd8b1b8e9 Add driver simulation model 2019-07-17 16:46:12 -07:00
Alex Forencich
ce011453d6 Add interface module 2019-07-17 16:43:12 -07:00
Alex Forencich
351404813a Add port module 2019-07-17 16:42:39 -07:00
Alex Forencich
65f0ff28b5 Add Ethernet interface module 2019-07-17 16:41:21 -07:00
Alex Forencich
12f215fe26 Add round robin transmit scheduler 2019-07-17 16:40:35 -07:00
Alex Forencich
bda4e87371 Add event management modules 2019-07-17 16:39:59 -07:00
Alex Forencich
f94e83e520 Add transmit and receive engines 2019-07-17 16:38:57 -07:00
Alex Forencich
6100e3ad78 Add RX checksum module and testbench 2019-07-16 00:42:49 -07:00
Alex Forencich
755c7959be merged changes in eth 2019-07-16 00:40:02 -07:00
Alex Forencich
021c91fcc7 Unconditionally wait at least one delta cycle 2019-07-16 00:37:20 -07:00
Alex Forencich
583849e0db merged changes in axis 2019-07-16 00:30:49 -07:00
Alex Forencich
1d5a4db0d5 Unconditionally wait at least one delta cycle 2019-07-16 00:30:19 -07:00
Alex Forencich
a653f2d839 Add TDMA scheduler module and testbench 2019-07-16 00:19:22 -07:00
Alex Forencich
fc9a6c1c50 Add completion queue manager module and testbench 2019-07-16 00:16:07 -07:00
Alex Forencich
46f653f097 Add queue manager module and testbench 2019-07-16 00:15:50 -07:00