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395 Commits 1 Branch 0 Tags
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7 Commits

Author SHA1 Message Date
Alex Forencich
d2c72d3583 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 22:28:05 -07:00
Alex Forencich
90959b8795 Add default_nettype none and resetall directives 2021-10-20 17:49:30 -07:00
Alex Forencich
bb74bdf2f7 Update pcie_axil_master module to support arbitrary memory operations 2021-10-03 11:46:55 -07:00
Alex Forencich
bc8715decc Hold read completions until pending writes complete 2021-09-25 00:46:55 -07:00
Alex Forencich
6af4461705 Fix length register widths and max value handling 2021-08-20 16:09:58 -07:00
Alex Forencich
1c424a8a51 Read locked is UR for PCIe endpoints 2021-08-06 01:39:11 -07:00
Alex Forencich
1a5e96d0fd Add PCIe AXI lite master module and testbench 2021-08-04 01:01:22 -07:00