356 Commits

Author	SHA1	Message	Date
Alex Forencich	43364943e1	merged changes in pcie	2021-08-20 16:10:32 -07:00
Alex Forencich	84e19ca305	Update file lists	2021-08-16 18:12:19 -07:00
Alex Forencich	fb241ae992	merged changes in pcie	2021-08-16 18:06:46 -07:00
Alex Forencich	38f766646b	Connect flow control signals to pcie_us_if	2021-08-12 00:05:43 -07:00
Alex Forencich	6517d43ee7	Add missing connection	2021-08-11 23:52:44 -07:00
Alex Forencich	09c90e321b	merged changes in pcie	2021-08-11 23:38:41 -07:00
Alex Forencich	a19474f9dd	Use AXI lite crossbar	2021-08-11 01:31:34 -07:00
Alex Forencich	07292b7dda	merged changes in axi	2021-08-11 01:28:07 -07:00
Alex Forencich	3e489fde27	Fix instance name	2021-08-04 12:37:13 -07:00
Alex Forencich	49aa27d1c5	Add placement constraints for AU50	2021-08-04 01:23:22 -07:00
Alex Forencich	0b65a1271a	Use new PCIe DMA modules	2021-08-04 01:20:57 -07:00
Alex Forencich	038772b175	merged changes in pcie	2021-08-04 01:07:22 -07:00
Alex Forencich	e0e34a9f0d	Update designs for PCIe module changes	2021-08-02 23:04:52 -07:00
Alex Forencich	6e178377c3	merged changes in pcie	2021-08-02 22:46:16 -07:00
Alex Forencich	b0ed724d70	merged changes in pcie	2021-07-25 02:24:33 -07:00
Alex Forencich	4ed99c6f87	Remove CMS IP version number	2021-07-03 00:09:10 -07:00
Alex Forencich	c926fd2ca1	Remove extraneous imports	2021-06-28 22:35:22 -07:00
minseongg	9af504a6c0	Update cmac_pad testbench	2021-06-28 22:33:57 -07:00
minseongg	8db2faddc6	Update cmac_pad testbench	2021-06-28 22:33:57 -07:00
minseongg	dc5c8232f9	Add cmac_pad testbench	2021-06-28 22:33:57 -07:00
Alex Forencich	b1c6bdbd88	merged changes in pcie	2021-06-27 14:05:12 -07:00
Alex Forencich	0a7f1ccbbe	Remove string parameters	2021-06-02 18:18:23 -07:00
Alex Forencich	4d89e70b92	merged changes in axi	2021-06-02 17:57:51 -07:00
Alex Forencich	bea7ff909f	merged changes in pcie	2021-06-02 17:57:45 -07:00
Alex Forencich	7558949e12	merged changes in eth	2021-06-02 17:57:39 -07:00
Alex Forencich	15cb21dbd1	Reorganize timing constraints	2021-05-20 15:24:01 -07:00
Alex Forencich	5ebc741ffe	merged changes in axi	2021-05-20 15:17:25 -07:00
Alex Forencich	955fdbf391	merged changes in pcie	2021-05-20 15:17:19 -07:00
Alex Forencich	892aa58004	merged changes in eth	2021-05-20 15:13:16 -07:00
Alex Forencich	7b2a0a1aed	Update testbenches	2021-04-28 20:54:44 -07:00
Alex Forencich	0916fb6686	Enable PTP on NetFPGA SUME	2021-04-01 21:58:32 -07:00
Alex Forencich	1bb5d8ab56	Add PTP support at 100G on VCU118	2021-04-01 18:02:58 -07:00
Alex Forencich	cf6e8bba99	Add PTP support at 100G on ADM-PCIE-9V3	2021-04-01 18:02:26 -07:00
Alex Forencich	d4b009b6d2	Add PTP support at 100G on VCU1525	2021-04-01 17:25:57 -07:00
Alex Forencich	2d20ee2807	Add PTP support at 100G on Alveo U50	2021-04-01 17:08:06 -07:00
Alex Forencich	275c0e98e9	Add PTP support at 100G on Alveo U250	2021-04-01 16:53:00 -07:00
Alex Forencich	77bb4b9dd8	Add PTP support at 100G on Alveo U200	2021-04-01 16:52:00 -07:00
Alex Forencich	2975e075d4	Add PTP support at 100G on Alveo U280	2021-04-01 16:31:23 -07:00
Alex Forencich	31c902685a	Add PTP support at 100G on fb2CG@KU15P	2021-04-01 16:29:52 -07:00
Alex Forencich	8b70695fa0	merged changes in eth	2021-03-30 22:25:28 -07:00
Alex Forencich	5d6723cc69	merged changes in pcie	2021-03-30 21:54:12 -07:00
Alex Forencich	c7896bef92	Use correct assignment type	2021-03-30 21:50:25 -07:00
Alex Forencich	2afbd1f15b	Enable PTP in 25G designs	2021-03-30 18:53:52 -07:00
Alex Forencich	1aeeb0bbe2	Update designs for PTP CDC and Ethernet MAC module changes	2021-03-30 16:41:31 -07:00
Alex Forencich	1c9430823b	merged changes in pcie	2021-03-30 16:20:33 -07:00
Alex Forencich	7993bc0125	merged changes in axi	2021-03-30 16:20:28 -07:00
Alex Forencich	f673470cf2	merged changes in eth	2021-03-30 16:20:04 -07:00
Alex Forencich	32abea89fa	Update testbenches	2021-03-06 20:30:25 -08:00
Alex Forencich	c620cd23e7	merged changes in pcie	2021-03-06 20:29:02 -08:00
Alex Forencich	48e1c39e3f	merged changes in eth	2021-03-06 20:27:23 -08:00