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84 Commits 1 Branch 0 Tags
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59 Commits

Author SHA1 Message Date
Alex Forencich
435f0b8749 Timing optimization of wstrb 2019-06-21 12:04:58 -07:00
Alex Forencich
834d6a4b2d Improve timing for unaligned operations (shift_axis_extra_cycle) 2019-06-15 21:27:41 -07:00
Alex Forencich
b0cda50aba Fix AXIL interconnect read bug 2019-06-12 17:57:39 -07:00
Alex Forencich
5581a76c0b Use correct clocks 2019-05-14 18:57:01 -07:00
Alex Forencich
7b33dde069 Fix state encoding 2019-05-06 17:37:09 -07:00
Alex Forencich
664949b7d6 Cleanup 2019-04-12 12:39:35 -07:00
Alex Forencich
685353c6e4 Rework AXI memory interfaces 2019-04-06 23:16:21 -07:00
Alex Forencich
a60e1f726f Fix use before define 2019-03-18 14:02:10 -07:00
Alex Forencich
f128190130 Ensure transfer is terminated at the end of the input frame 2019-03-13 14:48:05 -07:00
Alex Forencich
101be9fa2c Fix use before define 2019-03-12 13:15:11 -07:00
Alex Forencich
620526d581 Also match transfers by region 2019-03-12 12:58:56 -07:00
Alex Forencich
e71a62e6a1 Fix backpressure issue 2019-03-07 17:45:25 -08:00
Alex Forencich
4d628c9171 Fix thread matching 2019-03-06 13:40:29 -08:00
Alex Forencich
724f18113c Fix bug 2019-03-05 22:20:44 -08:00
Alex Forencich
e9cd97f0b4 Pass through more signals in AXI RAM interfaces 2019-02-26 01:25:03 -08:00
Alex Forencich
8478c5d076 Incorrect signals 2019-02-25 20:37:55 -08:00
Alex Forencich
7b713199ad Add AXI nonblocking crossbar interconnect module and testbench 2019-02-25 18:37:46 -08:00
Alex Forencich
365e063bc7 Add AXI DMA and CDMA descriptor mux modules 2019-02-25 15:44:10 -08:00
Alex Forencich
04dd6a34d7 Fix combinatorial loop 2019-02-20 18:48:27 -08:00
Alex Forencich
7654d874ae Fix out of range access due to off by one error 2019-02-11 19:30:57 -08:00
Alex Forencich
57dd292ae9 Add AXI RAM interface modules, AXI dual port RAM module, and testbench 2019-02-01 18:22:03 -08:00
Alex Forencich
787f198970 Add AXI lite dual-port RAM module and testbench 2019-01-17 17:48:23 -08:00
Alex Forencich
b1f40411ad Remove unnecessary reset 2019-01-17 17:09:55 -08:00
Alex Forencich
523bf689d8 Add optional output pipeline register to AXI lite RAM 2019-01-09 00:25:40 -08:00
Alex Forencich
513a53e52d Add AXI DMA module and testbench 2018-12-27 14:21:06 -08:00
Alex Forencich
41f8667310 Add AXI write DMA module and testbenches 2018-12-27 14:15:51 -08:00
Alex Forencich
50eb71221b Change cycle to segment, clean up parameters 2018-12-06 18:32:46 -08:00
Alex Forencich
76fba3ac84 Add AXI central DMA module and testbenches 2018-12-06 17:27:44 -08:00
Alex Forencich
275cb09205 Minor reorganization 2018-12-06 17:19:30 -08:00
Alex Forencich
e5e2aa8867 Use correct parameter 2018-12-06 01:21:42 -08:00
Alex Forencich
e7b6f43c8c Fix multi-driven net issue 2018-12-04 21:03:39 -08:00
Alex Forencich
7d0f3ef7a1 Fix address range overlap check to support arbitrary address widths 2018-12-04 17:00:26 -08:00
Alex Forencich
43234018cd Add AXI read DMA module and testbenches 2018-12-03 23:29:22 -08:00
Alex Forencich
61df54e62d Add M_REGIONS and M_SECURE parameters, add address range overlap check 2018-12-03 13:17:45 -08:00
Alex Forencich
7141a75ce8 Remove region inputs 2018-12-03 13:15:55 -08:00
Alex Forencich
b54d3eb866 Change cycle to segment, clean up parameters 2018-12-03 12:52:00 -08:00
Alex Forencich
0dbf0b1cff Add optional output pipeline register to AXI RAM module 2018-11-27 01:17:31 -08:00
Alex Forencich
b289e02fe4 Remove extraneous code 2018-08-26 14:06:57 -07:00
Alex Forencich
71427e7cf0 Update default parameters 2018-08-26 14:05:10 -07:00
Alex Forencich
07a4da3bea Fix connect logic 2018-08-23 16:20:58 -07:00
Alex Forencich
4f01dfb7d5 Support single slave interface 2018-08-23 14:43:57 -07:00
Alex Forencich
f1fb5b368c Fix connect logic 2018-08-23 14:41:40 -07:00
Alex Forencich
a25c4b17eb Add AXI shared interconnect and testbench 2018-08-22 23:42:31 -07:00
Alex Forencich
1753a2e6cf Remove extraneous logic 2018-08-22 22:28:15 -07:00
Alex Forencich
8427aa12bf Simplify request logic 2018-08-22 22:27:52 -07:00
Alex Forencich
0e36f647cb Add arbiter and priority encoder modules 2018-08-22 21:50:31 -07:00
Alex Forencich
e696abbdff Add AXI lite shared interconnect module and testbench 2018-08-22 20:34:31 -07:00
Alex Forencich
2a4c63e859 Change default address width to 32 2018-08-21 22:38:32 -07:00
Alex Forencich
6a002e2ce0 Add CONVERT_NARROW_BURST and FORWARD_ID parameters to AXI adapter 2018-08-20 23:23:00 -07:00
Alex Forencich
b15e8d9f63 Add AXI adapters and testbenchs 2018-08-20 19:10:08 -07:00