141 Commits

Author	SHA1	Message	Date
Alex Forencich	438a4fdcc9	Use FIFOs for PCIe tag management in PCIe read DMA modules	2021-02-28 19:34:24 -08:00
Alex Forencich	a3f805a0c3	Add pipeline register	2021-02-28 11:34:29 -08:00
Alex Forencich	92951723aa	Offset stored address by TLP byte length to eliminate updating stored address	2021-02-28 01:36:03 -08:00
Alex Forencich	603784b742	Fix operation init handling	2021-02-26 01:19:56 -08:00
Alex Forencich	912ef845a3	Rename tag to pcie_tag	2021-02-25 23:54:40 -08:00
Alex Forencich	062495b780	Remove redundant parameter PCIE_EXT_TAG_ENABLE	2021-02-25 18:20:08 -08:00
Alex Forencich	8294eecd65	Remove redundant parameter PCIE_TAG_WIDTH	2021-02-25 18:10:59 -08:00
Alex Forencich	8cfbe18335	Use FIFO for op tag management in PCIe read DMA modules	2021-02-25 16:30:23 -08:00
Alex Forencich	41d0e7cb7e	Minor optimization	2021-02-24 14:48:14 -08:00
Alex Forencich	63006e8092	Add output FIFO to DMA IF mux for read response data	2021-02-24 13:54:40 -08:00
Alex Forencich	ed29997a59	Add write done tracking to DMA IF mux	2021-02-24 13:51:50 -08:00
Alex Forencich	40a191a06d	Add output FIFO and write done tracking to ultrascale PCIe read DMA interface	2021-02-24 13:50:05 -08:00
Alex Forencich	9c8417799d	Add output FIFO and write done tracking to AXI stream sink DMA client	2021-02-24 13:48:56 -08:00
Alex Forencich	070689692d	Add wr_done signal to RAM model and placeholders to DMA components	2021-02-24 13:47:53 -08:00
Alex Forencich	057a93e07a	Sync data handling	2021-02-16 13:56:44 -08:00
Alex Forencich	33bc8c21ae	Fix bug in DMA client source when AXI stream width matches RAM interface width	2021-02-16 01:25:07 -08:00
Alex Forencich	20b2414d7a	Use reg instead of next for read operation generation	2021-02-15 00:09:03 -08:00
Alex Forencich	93e2769269	Make 64-bit-only states no-ops for other interface widths	2021-02-14 15:17:28 -08:00
Alex Forencich	a78674c06a	Refactor TLP header and tuser computation	2021-02-14 11:16:25 -08:00
Alex Forencich	fb1d64e710	Add pipeline stage to dma_if_pcie_us_wr	2021-02-12 16:58:35 -08:00
Alex Forencich	6d98a7c0e6	Ensure output FIFOs use distributed RAM	2021-02-11 00:14:36 -08:00
Alex Forencich	ba1b0ef20b	Add output FIFO to write DMA interface module	2021-02-10 17:29:17 -08:00
Alex Forencich	f76ed26503	Add output FIFO to AXI stream source DMA client	2021-02-10 17:28:08 -08:00
Alex Forencich	c6d8983fcd	Add wr_done output to DMA RAMs	2021-02-07 23:47:46 -08:00
Alex Forencich	7c19cb770d	Properly name registers, CQ demux bug fix	2020-12-19 14:09:56 -08:00
Alex Forencich	99e91c4d90	Fix pointer handling issue in PCIe AXI DMA write module	2020-12-18 18:37:53 -08:00
Alex Forencich	f567db764b	Rewrite 4K address boundary crossing checks	2020-11-11 23:54:39 -08:00
Alex Forencich	44955d2010	Make DMA RAM module synchronous and add async variant for improved RAM inference	2020-09-25 21:49:07 -07:00
Alex Forencich	d7f96eb104	Rewrite priority encoder to remove recusive construction	2020-08-17 18:30:40 -07:00
Alex Forencich	1e75c3cc70	Fix AXI stream DMA client bug causing dropped writes when widths are the same	2020-08-06 21:32:10 -07:00
Alex Forencich	0d4e9989c8	Fix asserts	2020-08-06 21:31:58 -07:00
Alex Forencich	8045992eb6	Remove extraneous code	2020-07-27 22:29:04 -07:00
Alex Forencich	1f523f0bb4	Remove unused reg	2020-07-26 21:39:10 -07:00
Alex Forencich	dd97d2d749	Minor refactoring	2020-07-25 22:09:30 -07:00
Alex Forencich	566dfa07e7	Read DMA timing optimizations	2020-03-26 14:34:48 -07:00
Alex Forencich	08d92fd138	Add pipeline stage for memory write generation to improve completion handling throughput	2020-03-24 21:58:48 -07:00
Alex Forencich	f8ce39c585	Timing optimization	2020-03-24 19:41:02 -07:00
Alex Forencich	37934485af	Timing optimization for ram_wrap computation	2020-02-28 13:22:35 -08:00
Alex Forencich	983610d6d9	Timing optimization for mask computation	2020-02-28 13:02:26 -08:00
Alex Forencich	50124ce66d	Timing optimization	2020-02-28 01:01:37 -08:00
Alex Forencich	db4d0a8f94	Timing optimizations	2020-02-27 20:00:37 -08:00
Alex Forencich	092c72ba66	Compute req_last_tlp in advance	2020-02-27 18:19:45 -08:00
Alex Forencich	18bf537f4f	Fix register size	2020-02-27 15:47:18 -08:00
Alex Forencich	a00589e5a3	Timing optimizations	2020-02-27 15:24:24 -08:00
Alex Forencich	ec2ceb8e56	Timing optimizations	2020-01-24 13:51:30 -08:00
Alex Forencich	e14f6c6f0e	Remove unused signals	2019-12-13 15:33:12 -08:00
Alex Forencich	dfd9744b3e	PCIe DMA write bandwidth optimizations	2019-12-13 15:31:37 -08:00
Alex Forencich	7567db1818	Add credit-based flow control to DMA cores	2019-12-06 23:24:36 -08:00
Alex Forencich	60a2813fbc	Fix indentation	2019-12-05 22:09:04 -08:00
Alex Forencich	f3a6cec13a	Use nonblocking assign	2019-12-03 15:47:58 -08:00