19 Commits

Author	SHA1	Message	Date
Ulrich Langenbach	984a58684c	fix partial initialisation of memory ... the fixed issue has been introduced in 0560f98e799d741d62522e61bf23321fc3f2880b	2022-03-24 15:50:25 -07:00
Ulrich Langenbach	0560f98e79	support more than 4k queues (workaround quartus loop iteration limit)	2021-12-16 12:09:39 -08:00
Alex Forencich	2aa9158d5c	Limit scheduler pipeline to a single AXI lite operation	2021-11-19 16:29:16 -08:00
Alex Forencich	f8a24d1c46	Add attributes to RAMs for proper synthesis in Quartus	2021-11-06 16:14:22 -07:00
Alex Forencich	7ac4797336	Add default_nettype none and resetall directives	2021-10-20 21:53:39 -07:00
Alex Forencich	454d237ab2	Rename parameter	2021-08-30 01:27:53 -07:00
Alex Forencich	0a7f1ccbbe	Remove string parameters	2021-06-02 18:18:23 -07:00
Alex Forencich	217217b45e	Remove unused table fields	2019-12-30 22:02:22 -08:00
Alex Forencich	db9e1df1fa	Update pipelining to enable URAM inference	2019-12-28 01:13:57 -08:00
Alex Forencich	45a33b8293	Fix scheduler bug	2019-12-16 14:13:01 -08:00
Alex Forencich	4dafedca27	Reschedule queue if necessary	2019-12-06 14:21:20 -08:00
Alex Forencich	f65b139797	Add scheduler control input to tx_scheduler_rr	2019-11-05 16:56:10 -08:00
Alex Forencich	8fa7e40507	Use new DMA subsystem	2019-10-17 16:02:14 -07:00
Alex Forencich	2e27d6ae2f	Improve tx_scheduler_rr timing	2019-09-14 23:32:34 -07:00
Alex Forencich	5048864d86	Update tx_scheduler to handle out of order operations	2019-09-02 09:02:53 -07:00
Alex Forencich	c9a17cdf90	Init scheduler queue state on reset	2019-08-13 13:51:50 -07:00
Alex Forencich	94c8dabad6	Rewrite scheduler	2019-08-13 00:45:01 -07:00
Alex Forencich	26f6774182	Parameter updates and documentation	2019-07-27 23:47:46 -07:00
Alex Forencich	12f215fe26	Add round robin transmit scheduler	2019-07-17 16:40:35 -07:00