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700 Commits 1 Branch 0 Tags
Commit Graph

10 Commits

Author SHA1 Message Date
Alex Forencich
451db171d1 Don't leave output floating 2019-07-19 18:13:30 -07:00
Alex Forencich
16d1662d98 Add PTP timestamping infrastructure to 10G MACs 2019-07-18 23:13:46 -07:00
Alex Forencich
3bd7be44fa Update FIFO instances and update MACs to use combined FIFO adapter module 2019-07-18 16:25:49 -07:00
Alex Forencich
134ce04777 Add configurable serdes pipeline register chain 2019-06-19 00:57:28 -07:00
Alex Forencich
79ec137243 Add PRBS31 generation and checking to 10G PHY 2019-05-10 20:28:45 -07:00
Alex Forencich
696c634726 Add rx_bad_block outputs 2019-04-17 00:16:45 -07:00
Alex Forencich
8285f94eaa Rename tx_sync regs 2019-03-28 16:27:33 -07:00
Alex Forencich
3eaed305f5 Connect TX underflow status outputs 2019-03-28 16:27:15 -07:00
Alex Forencich
585ccefa15 Add TX underflow error signal 2019-03-26 12:42:08 -07:00
Alex Forencich
ec38440d89 Add 10G Ethernet MAC/PHY combination modules and testbenches 2019-01-31 18:13:07 -08:00