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3 Commits

Author SHA1 Message Date
Alex Forencich
3a791afd37 Update DMA interface modules to support 512 bit interface 2019-10-14 16:23:18 -07:00
Alex Forencich
89ff925545 Timing optimizations 2019-10-14 14:00:55 -07:00
Alex Forencich
fdd7faef4f Add Xilinx Ultrascale PCIe DMA interface modules and testbenches 2019-10-12 23:03:42 -07:00