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8 Commits

Author SHA1 Message Date
Alex Forencich
24d179dd4a VCU118 XDC cleanup 2021-02-05 22:14:00 -08:00
Alex Forencich
b16fe8f7e7 More XDC clean up, add IO delay constraints for low speed IO 2021-02-05 16:08:23 -08:00
Alex Forencich
6476ad3fd0 Separate file for placement constraints 2021-01-14 14:42:58 -08:00
Alex Forencich
42e19e1e96 Add pipeline registers, floorplanning constraints for VCU118 100G design 2021-01-13 20:55:20 -08:00
Alex Forencich
993a712f01 Update VCU118 XDC 2020-10-06 00:41:45 -07:00
Alex Forencich
c2ded31ab7 Add QSPI flash access and IPROG for VCU118 2020-10-05 17:06:12 -07:00
Alex Forencich
e230fecb23 XDC clean up 2020-07-13 23:58:39 -07:00
Alex Forencich
ec03a36f98 Add 100G mqnic design for VCU118 2020-03-25 23:02:36 -07:00