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3 Commits

Author SHA1 Message Date
Alex Forencich
c62df81292 Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH 2022-02-15 00:39:46 -08:00
Alex Forencich
90959b8795 Add default_nettype none and resetall directives 2021-10-20 17:49:30 -07:00
Alex Forencich
292f73f43d Add DMA RAM demux modules 2021-08-16 18:03:38 -07:00