16 Commits

Author	SHA1	Message	Date
Alex Forencich	7fcec10961	Add internal RAM_DATA_WIDTH parameter	2022-04-01 01:11:30 -07:00
Alex Forencich	4bbd187567	Add statistics outputs to AXI DMA IF modules	2022-03-31 17:56:05 -07:00
Alex Forencich	2aeb820d35	Add operation table size assertion in AXI DMA IF modules	2022-03-31 16:42:46 -07:00
Alex Forencich	ac5f942128	Support error reporting in AXI DMA interface modules	2022-03-31 01:48:36 -07:00
Alex Forencich	0b9c7671fb	Minor refactor of zero-length handling logic	2022-03-31 00:05:55 -07:00
Alex Forencich	7cae50fa10	Support zero-length operations in AXI DMA interface modules	2022-03-30 23:40:02 -07:00
Alex Forencich	c62df81292	Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH	2022-02-15 00:39:46 -08:00
Alex Forencich	c47332462d	Implement USE_AXI_ID for dma_if_axi_rd	2022-02-01 16:29:56 -08:00
Alex Forencich	27f90934fe	Refactor to use existing variable	2022-02-01 16:27:13 -08:00
Alex Forencich	a0a7732801	Add missing resets	2022-02-01 16:26:12 -08:00
Alex Forencich	25f6dcb383	Fix alignment	2021-12-16 00:30:07 -08:00
Andreas Braun	01b97322c1	Fix reg to wire declaration ... Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>	2021-12-16 00:27:43 -08:00
Alex Forencich	b3145508ed	Remove debug code	2021-11-16 00:10:50 -08:00
Alex Forencich	d2c72d3583	Add attributes to RAMs for proper synthesis in Quartus	2021-11-02 22:28:05 -07:00
Alex Forencich	90959b8795	Add default_nettype none and resetall directives	2021-10-20 17:49:30 -07:00
Alex Forencich	e0167eedd8	Add AXI DMA interface modules and testbenches	2021-10-20 13:04:17 -07:00