228 Commits

Author	SHA1	Message	Date
Alex Forencich	070689692d	Add wr_done signal to RAM model and placeholders to DMA components	2021-02-24 13:47:53 -08:00
Alex Forencich	057a93e07a	Sync data handling	2021-02-16 13:56:44 -08:00
Alex Forencich	33bc8c21ae	Fix bug in DMA client source when AXI stream width matches RAM interface width	2021-02-16 01:25:07 -08:00
Alex Forencich	20b2414d7a	Use reg instead of next for read operation generation	2021-02-15 00:09:03 -08:00
Alex Forencich	93e2769269	Make 64-bit-only states no-ops for other interface widths	2021-02-14 15:17:28 -08:00
Alex Forencich	a78674c06a	Refactor TLP header and tuser computation	2021-02-14 11:16:25 -08:00
Alex Forencich	fb1d64e710	Add pipeline stage to dma_if_pcie_us_wr	2021-02-12 16:58:35 -08:00
Alex Forencich	6d98a7c0e6	Ensure output FIFOs use distributed RAM	2021-02-11 00:14:36 -08:00
Alex Forencich	ba1b0ef20b	Add output FIFO to write DMA interface module	2021-02-10 17:29:17 -08:00
Alex Forencich	f76ed26503	Add output FIFO to AXI stream source DMA client	2021-02-10 17:28:08 -08:00
Alex Forencich	c6d8983fcd	Add wr_done output to DMA RAMs	2021-02-07 23:47:46 -08:00
Alex Forencich	7c19cb770d	Properly name registers, CQ demux bug fix	2020-12-19 14:09:56 -08:00
Alex Forencich	99e91c4d90	Fix pointer handling issue in PCIe AXI DMA write module	2020-12-18 18:37:53 -08:00
Alex Forencich	f567db764b	Rewrite 4K address boundary crossing checks	2020-11-11 23:54:39 -08:00
Alex Forencich	44955d2010	Make DMA RAM module synchronous and add async variant for improved RAM inference	2020-09-25 21:49:07 -07:00
Alex Forencich	d7f96eb104	Rewrite priority encoder to remove recusive construction	2020-08-17 18:30:40 -07:00
Alex Forencich	1e75c3cc70	Fix AXI stream DMA client bug causing dropped writes when widths are the same	2020-08-06 21:32:10 -07:00
Alex Forencich	0d4e9989c8	Fix asserts	2020-08-06 21:31:58 -07:00
Alex Forencich	8045992eb6	Remove extraneous code	2020-07-27 22:29:04 -07:00
Alex Forencich	1f523f0bb4	Remove unused reg	2020-07-26 21:39:10 -07:00
Alex Forencich	dd97d2d749	Minor refactoring	2020-07-25 22:09:30 -07:00
Alex Forencich	566dfa07e7	Read DMA timing optimizations	2020-03-26 14:34:48 -07:00
Alex Forencich	08d92fd138	Add pipeline stage for memory write generation to improve completion handling throughput	2020-03-24 21:58:48 -07:00
Alex Forencich	f8ce39c585	Timing optimization	2020-03-24 19:41:02 -07:00
Alex Forencich	37934485af	Timing optimization for ram_wrap computation	2020-02-28 13:22:35 -08:00
Alex Forencich	983610d6d9	Timing optimization for mask computation	2020-02-28 13:02:26 -08:00
Alex Forencich	50124ce66d	Timing optimization	2020-02-28 01:01:37 -08:00
Alex Forencich	db4d0a8f94	Timing optimizations	2020-02-27 20:00:37 -08:00
Alex Forencich	092c72ba66	Compute req_last_tlp in advance	2020-02-27 18:19:45 -08:00
Alex Forencich	18bf537f4f	Fix register size	2020-02-27 15:47:18 -08:00
Alex Forencich	a00589e5a3	Timing optimizations	2020-02-27 15:24:24 -08:00
Alex Forencich	ec2ceb8e56	Timing optimizations	2020-01-24 13:51:30 -08:00
Alex Forencich	e14f6c6f0e	Remove unused signals	2019-12-13 15:33:12 -08:00
Alex Forencich	dfd9744b3e	PCIe DMA write bandwidth optimizations	2019-12-13 15:31:37 -08:00
Alex Forencich	7567db1818	Add credit-based flow control to DMA cores	2019-12-06 23:24:36 -08:00
Alex Forencich	60a2813fbc	Fix indentation	2019-12-05 22:09:04 -08:00
Alex Forencich	f3a6cec13a	Use nonblocking assign	2019-12-03 15:47:58 -08:00
Alex Forencich	8985c6dbf3	Add RQ sequence number inputs, operation table, TX_LIMIT parameter to ultrascale write DMA modules	2019-12-03 15:46:36 -08:00
Alex Forencich	a1d0fb810f	Reorganize	2019-12-02 15:27:27 -08:00
Alex Forencich	2afef8c6d8	Fix use before define	2019-12-02 15:18:08 -08:00
Alex Forencich	80dafd5870	Check FIFO depth	2019-12-02 15:15:24 -08:00
Alex Forencich	2dbe6e19ab	Reset mask FIFO pointers	2019-12-02 14:07:17 -08:00
Alex Forencich	546ef162dd	Rewrite reset	2019-11-26 16:44:46 -08:00
Alex Forencich	4c8fcef230	Add RQ sequence number inputs, TX_LIMIT parameter to ultrascale read DMA modules	2019-11-26 16:30:30 -08:00
Alex Forencich	bbcdcc17bc	Rename OP_TAG_WIDTH to OP_TABLE_SIZE	2019-11-25 14:59:53 -08:00
Alex Forencich	ee532a2472	Check tag count based on target device	2019-11-15 14:57:23 -08:00
Alex Forencich	52c502227f	Remove unused client tag ports and parameters	2019-11-15 00:55:13 -08:00
Alex Forencich	c43a3eb41a	Fix latch inference	2019-10-22 16:03:58 -07:00
Alex Forencich	458a7fc598	Prioritize read request passthrough	2019-10-20 23:30:16 -07:00
Alex Forencich	771c3af93f	Remove debug code	2019-10-20 23:21:21 -07:00