20 Commits

Author	SHA1	Message	Date
Alex Forencich	489506e4c0	Add FPGA ID register	2019-11-17 12:46:27 -08:00
Alex Forencich	33be402b16	Update widths	2019-11-14 00:02:10 -08:00
Alex Forencich	e43c011e33	Update testbenches	2019-11-05 18:31:41 -08:00
Alex Forencich	736321641f	Parametrize addressing	2019-10-31 23:24:42 -07:00
Alex Forencich	02cc2c7377	Use PCIe gen 3 x16	2019-10-17 19:02:46 -07:00
Alex Forencich	1a06f16130	Update VCU118 XDC file	2019-10-17 16:07:42 -07:00
Alex Forencich	8fa7e40507	Use new DMA subsystem	2019-10-17 16:02:14 -07:00
Alex Forencich	9ab0d50c0a	Add PCIe interface tuser width parameters	2019-10-05 13:56:24 -07:00
Alex Forencich	9a1a58f608	Add PCIe interface tuser width parameters	2019-10-04 16:51:07 -07:00
Alex Forencich	2c46513837	Update designs	2019-09-23 18:21:54 -07:00
Alex Forencich	835abf9412	Remove pcie_us_axi_master instances and corresponding BAR	2019-09-19 17:31:59 -07:00
Alex Forencich	b5868c8997	Update PTP perout support in VCU108 and VCU118 designs	2019-09-18 19:46:45 -07:00
Alex Forencich	132d44cd90	Increase crossbar threads count	2019-09-11 18:06:14 -07:00
Alex Forencich	d67c9ff70e	Pull out scheduler op table size parameter	2019-08-23 07:44:33 -07:00
Alex Forencich	a4132cfda7	Integrate TX checksum offload	2019-08-22 00:45:09 -07:00
Alex Forencich	94c8dabad6	Rewrite scheduler	2019-08-13 00:45:01 -07:00
Alex Forencich	80f06e1fcc	Update testbenches	2019-08-13 00:39:28 -07:00
Alex Forencich	2fbbfb05f9	Parametrize channel assignments	2019-07-28 16:02:54 -07:00
Alex Forencich	26f6774182	Parameter updates and documentation	2019-07-27 23:47:46 -07:00
Alex Forencich	089a46c811	Add VCU118 mqnic design	2019-07-25 20:21:11 -07:00