172 Commits

Author	SHA1	Message	Date
Alex Forencich	670dfa0d11	Fix pcie_us_axi_dma_wr testbench file list	2021-02-28 19:50:45 -08:00
Alex Forencich	5715e12d41	Remove tag manager module	2021-02-28 19:37:16 -08:00
Alex Forencich	438a4fdcc9	Use FIFOs for PCIe tag management in PCIe read DMA modules	2021-02-28 19:34:24 -08:00
Alex Forencich	062495b780	Remove redundant parameter PCIE_EXT_TAG_ENABLE	2021-02-25 18:20:08 -08:00
Alex Forencich	8294eecd65	Remove redundant parameter PCIE_TAG_WIDTH	2021-02-25 18:10:59 -08:00
Alex Forencich	6fb2eb6b4e	Remove unnecessary delays from testbenches	2021-02-24 13:50:45 -08:00
Alex Forencich	070689692d	Add wr_done signal to RAM model and placeholders to DMA components	2021-02-24 13:47:53 -08:00
Alex Forencich	742ef1c272	Add same-width test cases to DMA clients	2021-02-16 01:26:05 -08:00
Alex Forencich	93496729f3	Update testbench	2021-02-12 16:59:13 -08:00
Alex Forencich	5f7697178b	Remove await ReadOnly	2021-02-10 18:42:32 -08:00
Alex Forencich	87a6efe05c	Rework sim_build output directory, fix default makefile target	2020-12-29 16:26:48 -08:00
Alex Forencich	a0a5ccc0a4	Add cocotb testbenches	2020-12-19 14:10:57 -08:00
Alex Forencich	dc48d86b99	Improve BAR initialization	2020-07-24 22:54:55 -07:00
Alex Forencich	ebae4e436d	Update AXI simulation model	2020-07-02 21:28:35 -07:00
Alex Forencich	060320010d	Don't configure MSI if already configured	2020-03-02 21:16:09 -08:00
Alex Forencich	a6d64bbcbb	Remove extraneous character	2019-12-07 14:36:32 -08:00
Alex Forencich	d561195dc8	Add get_data_credits to TLP	2019-12-07 00:54:16 -08:00
Alex Forencich	7567db1818	Add credit-based flow control to DMA cores	2019-12-06 23:24:36 -08:00
Alex Forencich	00858212c6	Placeholder values for flow control credit outputs	2019-12-06 19:16:05 -08:00
Alex Forencich	8985c6dbf3	Add RQ sequence number inputs, operation table, TX_LIMIT parameter to ultrascale write DMA modules	2019-12-03 15:46:36 -08:00
Alex Forencich	a7be8e8f87	Clear the sequence number valid bits	2019-11-27 16:43:15 -08:00
Alex Forencich	4c8fcef230	Add RQ sequence number inputs, TX_LIMIT parameter to ultrascale read DMA modules	2019-11-26 16:30:30 -08:00
Alex Forencich	c5a0d05b47	Add OP_TABLE_SIZE parameter to testbenches	2019-11-26 00:00:49 -08:00
Alex Forencich	e7bd0a62f1	Implement RQ sequence numbers in Ultrascale models	2019-11-25 18:07:49 -08:00
Alex Forencich	bbcdcc17bc	Rename OP_TAG_WIDTH to OP_TABLE_SIZE	2019-11-25 14:59:53 -08:00
Alex Forencich	176e1159a3	Update python parameter computation to match verilog clog2	2019-11-24 00:01:33 -08:00
Alex Forencich	f6f8e556ef	Update tag parameters	2019-11-23 21:18:46 -08:00
Alex Forencich	6c6e3c8212	Remove extraneous parameter connections	2019-11-23 21:15:33 -08:00
Alex Forencich	b2c5004962	Fix discontinue masks	2019-11-23 00:20:21 -08:00
Alex Forencich	52c502227f	Remove unused client tag ports and parameters	2019-11-15 00:55:13 -08:00
Alex Forencich	34c97150e8	Fix get_free_tag	2019-11-04 14:11:24 -08:00
Alex Forencich	3a791afd37	Update DMA interface modules to support 512 bit interface	2019-10-14 16:23:18 -07:00
Alex Forencich	553d7e05fe	Update AXI DMA modules to support 512 bit interface	2019-10-14 16:22:09 -07:00
Alex Forencich	f8bc6c31e5	Update AXI master modules to support 512 bit interface	2019-10-14 16:20:46 -07:00
Alex Forencich	af09059248	Update AXI lite master module to support 512 bit interface	2019-10-14 15:58:38 -07:00
Alex Forencich	39200d84cb	Update simulation models to support 512 bit interface	2019-10-14 15:45:41 -07:00
Alex Forencich	2c43a6e189	Use mmap objects instead of bytearrays	2019-10-13 15:41:12 -07:00
Alex Forencich	fdd7faef4f	Add Xilinx Ultrascale PCIe DMA interface modules and testbenches	2019-10-12 23:03:42 -07:00
Alex Forencich	e1035ed57d	Add AXI stream sink DMA client module and testbench	2019-10-12 22:35:57 -07:00
Alex Forencich	baeeb8ea5c	Add AXI stream source DMA client module and testbench	2019-10-12 22:34:15 -07:00
Alex Forencich	5e9254d519	Check is_eof_0 in RCSink	2019-10-12 18:58:27 -07:00
Alex Forencich	9b5a5db4d1	Add USPcieFrame intermediate format	2019-10-12 18:01:39 -07:00
Alex Forencich	603a6e18e2	Fix RC channel sideband byte enables	2019-10-11 14:16:44 -07:00
Alex Forencich	b7a505acfd	Add segmented DMA RAM simulation model	2019-10-08 15:14:32 -07:00
Alex Forencich	295b6a507e	Use constants instead of magic numbers	2019-10-01 17:30:09 -07:00
Alex Forencich	3817736aa1	Use constants instead of magic numbers	2019-10-01 17:24:18 -07:00
Alex Forencich	1b91200a4a	Implement error code	2019-10-01 17:17:42 -07:00
Alex Forencich	b2d9a6a77f	Add constants	2019-10-01 17:15:15 -07:00
Alex Forencich	836246ec4d	Add missing asserts	2019-09-29 12:55:53 -07:00
Alex Forencich	e97e4ad423	Parametrize tuser signal widths	2019-09-26 23:30:03 -07:00