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Author SHA1 Message Date
Alex Forencich
a443e8862c Update TCL timing constraints to handle clocks from OOC IP that are not constrained during synthesis 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-26 14:59:19 -07:00
Alex Forencich
4f7c0ebe2a merged changes in axis 2023-07-26 14:53:57 -07:00
Alex Forencich
9bc052de8b Another update to async FIFO timing constraints to deal with OOC clock constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-26 14:53:01 -07:00
Alex Forencich
6a6d1f0ac0 fpga/mqnic: Clean up some aditional file headers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-26 00:51:23 -07:00
Alex Forencich
02ce168c63 Improve PTP-related tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-24 01:01:54 -07:00
Alex Forencich
fa173f93e5 Avoid testbench reset during alignment test 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-24 00:57:43 -07:00
Alex Forencich
70cc19ff15 Add MAC control layer to core 1G and 10G MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-23 22:24:42 -07:00
Alex Forencich
78284572ef Remove XDC constraints that do not apply to Artix 7 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-23 18:35:22 -07:00
Alex Forencich
ba5a883433 Add pause/PFC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-23 16:31:33 -07:00
Alex Forencich
6d5cda5986 Add MAC control layer modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-22 00:47:15 -07:00
Alex Forencich
b1177eb4ed Rename HXT100G to HTG-640 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 18:17:26 -07:00
Alex Forencich
5d349c9cb2 Enable overtemp shutdown in constraints files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 18:17:12 -07:00
Alex Forencich
f4a8561652 Add HTG-9200 + HTG 6x QSFP28 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 18:16:59 -07:00
Alex Forencich
6bf727d3ef Add VCU118 + HTG 6x QSFP28 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 18:16:20 -07:00
Alex Forencich
31901754a6 Add FMC pins to VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:55:55 -07:00
Alex Forencich
19a76cbaf9 Add FMC pins to VCU108 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:55:44 -07:00
Alex Forencich
72a35c08ef Clean up FMC+ pins on HTG-9200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:55:19 -07:00
Alex Forencich
bdc974a60c Reorganize HTG-9200 PLL config 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:34:11 -07:00
Alex Forencich
efb3747967 Add IO delay false paths to HTG-9200 constraints file 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-20 21:15:20 -07:00
Alex Forencich
4a65e3594c Connect all PLL control lines on HTG-9200 board 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-20 01:17:49 -07:00
Alex Forencich
789512c6da fpga/mqnic/VCU118: Use QSFP Si570 for both QSFP modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-19 17:49:46 -07:00
Alex Forencich
375b12865f Use QSFP Si570 for both QSFP modules on VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-19 17:00:33 -07:00
Alex Forencich
7d2f77a30b fpga/common: Connect xcvr_ctrl_rst to QPLLs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 18:44:42 -07:00
Alex Forencich
a99815800b fpga/common: Fix GT wrapper timing constraints when DRP interface is tied off 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 18:43:07 -07:00
Alex Forencich
1be196279f Fix FIFO instances in S10DX example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 11:05:24 -07:00
Alex Forencich
2858aaaef7 Add TX PTP timestamp enable bit in tuser 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 10:58:40 -07:00
Alex Forencich
50b6f53387 Update testbench clock frequencies 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-15 01:53:31 -07:00
Alex Forencich
d3fb11b2c3 Use unified 10G/25G design for HTG9200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 21:35:42 -07:00
Alex Forencich
412df8fea0 Use unified 10G/25G design for fb2CG@KU15P 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 21:34:53 -07:00
Alex Forencich
026a302c1c Use unified 10G/25G design for ExaNIC X25 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:45:47 -07:00
Alex Forencich
5dc38f11b7 Use unified 10G/25G design for Alveo VCU1525 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:42:40 -07:00
Alex Forencich
a221adc468 Use unified 10G/25G design for Alveo U50 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:40:38 -07:00
Alex Forencich
147435dfe1 Use unified 10G/25G design for Alveo U280 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:38:34 -07:00
Alex Forencich
ea80d853ed Use unified 10G/25G design for Alveo U250 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 19:53:21 -07:00
Alex Forencich
0b18633bb1 Use unified 10G/25G design for Alveo U200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 19:49:25 -07:00
Alex Forencich
489ee73355 Use unified 10G/25G design for VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 19:02:57 -07:00
Alex Forencich
729c5a61ce Use unified 10G/25G design for ADM-PCIE-9V3 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 18:59:33 -07:00
Alex Forencich
48cbe43fa7 Update Vivado makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 18:48:34 -07:00
Alex Forencich
ed4a26e2cb Update Vivado makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 18:45:01 -07:00
Alex Forencich
b6a9092a9f Update makefiles for Intel devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 17:46:34 -07:00
Alex Forencich
c4376c8674 Update XDC files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 17:12:32 -07:00
Alex Forencich
17443e9366 fpga/mqnic: Separate event and completion write instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-10 17:53:03 -07:00
Alex Forencich
bed12ee774 Consolidate CQs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-10 17:52:34 -07:00
Alex Forencich
905e6c6358 Add PTP timestamping tests for 1G MAC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-08 01:41:35 -07:00
Alex Forencich
9665df8a44 Fix PTP timestamping in 1G MAC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-08 01:41:14 -07:00
Alex Forencich
265035769a Reorganize queue control registers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-07 01:19:19 -07:00
Alex Forencich
56c89640e0 scripts: Add mqnic_ddcmd.sh script to control dynamic debug statements 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-07 01:11:37 -07:00
Alex Forencich
fa75b47b7b modules/mqnic: Convert more relatively frequent info-level printk calls to debug-level so they can be selectively enabled via dynamic debug 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-07 01:10:49 -07:00
Joachim Foerster
1d729817a6 modules/mqnic: Turn "TX ring ... full ..." message into netdev-related debug message 
To not overwhelm any logging daemon. Full TX queues can be quite common
depending on a system's context and capabilities. Mostly all the details are not
required anyway in such cases.

To enable such debug messages and have their text turn up in dmesg and logging
daemons, the mqnic module has to be compiled with CPP symbol DEBUG being (`make
DEBUG=yes`) defined, or the kernel in use has to support "Dynamic Debug" [1]. In
the latter case all such debug messages in module mqnic can be enabled with:

echo 'module mqnic +pflmt' | sudo tee /sys/kernel/debug/dynamic_debug/control

To enable just this specific messages, based on its (partial) format:

echo 'format "TX ring %d full" +pflmt' | sudo tee /sys/kernel/debug/dynamic_debug/control

[1] https://www.kernel.org/doc/html/latest/admin-guide/dynamic-debug-howto.html

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2023-07-07 00:30:52 -07:00
Joachim Foerster
6a975f3433 modules/mqnic/Makefile: Define CPP symbol DEBUG when environment variable DEBUG is provided 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2023-07-07 00:30:52 -07:00