Alex Forencich
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3bd7be44fa
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Update FIFO instances and update MACs to use combined FIFO adapter module
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2019-07-18 16:25:49 -07:00 |
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Alex Forencich
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d2fedc4134
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Rename ports
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2018-11-07 22:35:06 -08:00 |
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Alex Forencich
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470ab887d9
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Update mux instances
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2018-11-01 00:59:14 -07:00 |
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Alex Forencich
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5b7646ccda
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Rework ARP subsystem
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2018-06-18 13:59:58 -07:00 |
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Alex Forencich
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0fd157964a
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Happy new year
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2018-02-26 12:50:51 -08:00 |
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Alex Forencich
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77211926f2
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Fix classifier logic
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2017-06-09 21:27:29 -07:00 |
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Alex Forencich
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9b2ac9dfc1
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Happy new year
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2017-05-18 13:47:45 -07:00 |
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Alex Forencich
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270641b7a3
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Update UDP modules and example designs to utilize UDP checksum modules
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2016-09-30 22:15:21 -07:00 |
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Alex Forencich
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9c01e114b4
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Happy new year
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2016-01-05 00:34:32 -08:00 |
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Alex Forencich
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a98dfce099
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Update output registers, remove extraneous resets, fix constant widths
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2015-11-09 23:50:34 -08:00 |
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Alex Forencich
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14e71d568d
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Improve classifier logic by registering payload select signals
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2015-02-28 19:14:22 -08:00 |
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Alex Forencich
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b892fd1172
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Add UDP complete module and testbench
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2015-02-26 22:57:24 -08:00 |
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