13 Commits

Author	SHA1	Message	Date
Alex Forencich	c62df81292	Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH	2022-02-15 00:39:46 -08:00
Alex Forencich	90959b8795	Add default_nettype none and resetall directives	2021-10-20 17:49:30 -07:00
Alex Forencich	36ec7aaa16	Add error reporting to DMA modules	2021-08-02 17:24:00 -07:00
Alex Forencich	062495b780	Remove redundant parameter PCIE_EXT_TAG_ENABLE	2021-02-25 18:20:08 -08:00
Alex Forencich	8294eecd65	Remove redundant parameter PCIE_TAG_WIDTH	2021-02-25 18:10:59 -08:00
Alex Forencich	070689692d	Add wr_done signal to RAM model and placeholders to DMA components	2021-02-24 13:47:53 -08:00
Alex Forencich	7567db1818	Add credit-based flow control to DMA cores	2019-12-06 23:24:36 -08:00
Alex Forencich	8985c6dbf3	Add RQ sequence number inputs, operation table, TX_LIMIT parameter to ultrascale write DMA modules	2019-12-03 15:46:36 -08:00
Alex Forencich	bbcdcc17bc	Rename OP_TAG_WIDTH to OP_TABLE_SIZE	2019-11-25 14:59:53 -08:00
Alex Forencich	ee532a2472	Check tag count based on target device	2019-11-15 14:57:23 -08:00
Alex Forencich	b0c97e8d23	Add missing parameter connection	2019-10-14 23:52:38 -07:00
Alex Forencich	3a791afd37	Update DMA interface modules to support 512 bit interface	2019-10-14 16:23:18 -07:00
Alex Forencich	fdd7faef4f	Add Xilinx Ultrascale PCIe DMA interface modules and testbenches	2019-10-12 23:03:42 -07:00