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28 Commits

Author SHA1 Message Date
Alex Forencich
c5d5fe8a64 fpga/mqnic: Remove unused wires 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-09 23:02:44 -07:00
Alex Forencich
f082196b4a Expose EVENT_QUEUE_INDEX_WIDTH parameter at top-level 2022-03-29 23:15:06 -07:00
Alex Forencich
cbd9d0dfc6 Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports 2022-03-28 17:23:27 -07:00
Alex Forencich
09128df360 Add SCHED_PER_IF parameter to split scheduler count from port count 2022-03-28 15:20:33 -07:00
Alex Forencich
dfae34ed25 Pass through PTP pipelining settings 2022-03-28 00:50:29 -07:00
Alex Forencich
e95c132045 Route PCIe user reset through BUFG 2022-03-25 01:26:29 -07:00
Alex Forencich
e9d52516fb Unified 10G/25G design for ExaNIC X25 2022-03-14 19:12:58 -07:00
Alex Forencich
8168469ec8 Update config.tcl 2022-03-14 14:45:38 -07:00
Alex Forencich
d9e79c9923 Rename cores to match transceiver type 2022-03-03 22:41:34 -08:00
Alex Forencich
7bbc777c98 Update ExaNIC X25 to use new wrapper 2022-03-03 15:32:17 -08:00
Alex Forencich
2909d205de Remove unused files 2022-02-16 17:40:28 -08:00
Alex Forencich
3997e0d95b Parametriztion updates, add RAM_ADDR_WIDTH as a top-level parameter 2022-02-15 18:01:43 -08:00
Alex Forencich
627ac359d5 Add layer 2 ingress/egress modules 2022-02-13 23:09:41 -08:00
Alex Forencich
b7bc240aa6 Add JTAG and GPIO passthroughs to application section 2022-01-27 23:06:05 -08:00
Alex Forencich
aab30c8cd0 Add transceiver quad wrappers 2022-01-16 18:28:22 -08:00
Alex Forencich
335a5e890b Initial implementation of shared interface datapath 2021-12-31 14:33:31 -08:00
Alex Forencich
ce21774f06 Register space reorganization 2021-12-29 22:31:46 -08:00
Alex Forencich
8548e8570f Update vivado.mk 2021-12-20 22:03:06 -08:00
Alex Forencich
7a43618e3c Use start_soon instead of fork 2021-12-10 20:43:21 -08:00
Alex Forencich
886111c9e6 Update 10G designs for PTP separate RX clock 2021-11-19 01:52:23 -08:00
Alex Forencich
af3b6312a9 Add PTP_USE_SAMPLE_CLOCK parameter to testbenches 2021-11-18 21:12:06 -08:00
Alex Forencich
5bf9de656c Update testbenches 2021-11-17 18:08:40 -08:00
Alex Forencich
38c85a6bcd Set subsystem ID based on board, remove unnecessary configuration settings 2021-11-02 15:32:55 -07:00
Alex Forencich
5eca6389cf Rework GT instances in ExaNIC X25 10G and 25G designs 2021-10-21 16:29:48 -07:00
Alex Forencich
7ac4797336 Add default_nettype none and resetall directives 2021-10-20 21:53:39 -07:00
Alex Forencich
607257d7bb Fix connections 2021-10-20 20:43:11 -07:00
Alex Forencich
982edfeda7 Update file lists 2021-10-20 19:37:37 -07:00
Alex Forencich
780406197d Add 25G mqnic design for ExaNIC X25 2021-09-26 18:11:00 -07:00