61 Commits

Author	SHA1	Message	Date
Alex Forencich	4c4119d44a	Use more correct parameters	2019-09-30 22:36:06 -07:00
Alex Forencich	7197e17445	Remove redundant code	2019-09-29 12:57:48 -07:00
Alex Forencich	e97e4ad423	Parametrize tuser signal widths	2019-09-26 23:30:03 -07:00
Alex Forencich	8678ecee65	Fix bug in AXI operation generation	2019-09-26 23:25:09 -07:00
Alex Forencich	e365ae44da	Move AXI transfer size logic to improve timing	2019-09-26 14:39:31 -07:00
Alex Forencich	cddac11486	Bypass check when unnecessary	2019-09-26 14:38:21 -07:00
Alex Forencich	8f73b5605f	Fix check	2019-09-26 14:37:41 -07:00
Alex Forencich	e3ad96ef07	Add RQ channel passthrough to pcie_us_axi_dma_wr to eliminiate external mux	2019-09-17 16:32:47 -07:00
Alex Forencich	68974e800b	Fix completion handling bug	2019-08-19 14:31:08 -07:00
Alex Forencich	f518aec219	Include instance names in error messages	2019-07-25 16:38:54 -07:00
Alex Forencich	c75f29c648	Add parameter documentation	2019-07-24 18:01:13 -07:00
Alex Forencich	7c500e6b6e	Update axis_arb_mux	2019-07-24 17:52:53 -07:00
Alex Forencich	8f36c4a216	Update priority encoder	2019-07-24 14:23:04 -07:00
Alex Forencich	8ecf4a22ef	Add pcie_us_cfg module	2019-07-13 10:24:25 -07:00
Alex Forencich	0515d354e3	Critical path optimization	2019-06-28 17:28:12 -07:00
Alex Forencich	4afbd71f1f	Fanout optimization	2019-06-28 17:24:37 -07:00
Alex Forencich	db8a2e1e96	Parametrize cycle count widths	2019-05-13 22:06:41 -07:00
Alex Forencich	74a75772ec	Pipeline tag table write	2019-05-13 19:15:43 -07:00
Alex Forencich	c1c4971d73	Use correct variable	2019-04-09 17:54:04 -07:00
Alex Forencich	f53b7ab75e	Fix MSI wrapper	2019-03-27 17:42:37 -07:00
Alex Forencich	5d42112477	Enable PCIe extended tag based on tag count	2019-03-21 00:01:48 -07:00
Alex Forencich	b592c7d7af	Add missing parameter	2019-03-03 22:32:35 -08:00
Alex Forencich	56ebc966e1	Update parameters	2019-03-03 13:37:34 -08:00
Alex Forencich	201c5faa80	Always ready on RC channel in idle for 64 bits	2019-01-22 23:00:17 -08:00
Alex Forencich	4422b908bf	Backpressure for awvalid	2019-01-22 22:54:40 -08:00
Alex Forencich	fac972bfe6	RC channel backpressure fix	2019-01-22 22:50:15 -08:00
Alex Forencich	263bb5c670	Index based on correct tag value	2019-01-22 22:47:15 -08:00
Alex Forencich	d86fb594c5	More fixes for tlp_cmd backpressure	2019-01-12 00:37:38 -08:00
Alex Forencich	5c24dcc1df	Ensure tlp_cmd registers are clear when generating a new request	2019-01-11 01:27:52 -08:00
Alex Forencich	5cf9597201	Only generate a request if a tag is available	2019-01-10 19:00:19 -08:00
Alex Forencich	852d583282	Only store value when it is transferred	2019-01-02 01:59:29 -08:00
Alex Forencich	9b572ad0ac	Fix bug	2019-01-02 01:59:05 -08:00
Alex Forencich	0a33ed17a7	Use correct parameter	2018-12-27 21:53:45 -08:00
Alex Forencich	c7958e1689	Add PCIe AXI DMA descriptor mux module	2018-12-27 19:02:15 -08:00
Alex Forencich	fbec32e4f2	Use whole status FIFO memory	2018-12-06 17:36:12 -08:00
Alex Forencich	5db9cddf6e	Reorganize and simplify burst length computation code	2018-11-29 15:20:01 -08:00
Alex Forencich	8ab02e4220	Remove some debug code	2018-11-28 11:14:26 -08:00
Alex Forencich	89c8e87f95	Add status FIFO to manage write responses	2018-11-28 11:13:53 -08:00
Alex Forencich	c6f342ef01	Respect enable signal	2018-11-28 01:18:48 -08:00
Alex Forencich	89c52d4eec	Fix bit width warning	2018-11-26 23:27:06 -08:00
Alex Forencich	061756f667	Add AXI stream mux module	2018-11-26 23:25:46 -08:00
Alex Forencich	28fa143ae5	Add Ultrascale PCIe DMA modules and testbenches	2018-11-26 23:23:54 -08:00
Alex Forencich	008a7167c7	Add AXI_MAX_BURST_SIZE parameter to PCIe AXI master	2018-11-26 18:03:54 -08:00
Alex Forencich	d81ee9487a	Add some more comments	2018-11-26 15:56:13 -08:00
Alex Forencich	24f709573c	Only store on valid transfer in	2018-11-26 13:18:38 -08:00
Alex Forencich	1dcc091201	Adjustments for 64 bit datapath	2018-11-26 13:17:41 -08:00
Alex Forencich	8c7eb13c0d	Properly handle truncated packet	2018-11-26 13:12:50 -08:00
Alex Forencich	a6809a6b57	Use constants instead of magic numbers	2018-11-26 13:07:50 -08:00
Alex Forencich	c3d4aeda48	Use logical operators	2018-11-08 23:36:05 -08:00
Alex Forencich	038688a223	Add priority encoder and arbiter modules	2018-10-29 17:55:47 -07:00